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作 者:张沛鑫 张南[1] 王大庆[2] 吴桐 李哲[1] 宫丰奎[1] ZHANG Peixin;ZHANG Nan;WANG Daqing;WU Tong;LI Zhe;GONG Fengkui(State Key Laboratory of Integrated Service Networks,Xidian University,Xi’an 710071,China;CAST-Xi’an Institute of Space Radio Technology,Xi’an 710100,China)
机构地区:[1]西安电子科技大学空天地一体化综合业务网全国重点实验室,陕西西安710071 [2]西安空间无线电技术研究所,陕西西安710100
出 处:《通信学报》2023年第4期15-26,共12页Journal on Communications
基 金:国家自然科学基金资助项目(No.62001354)。
摘 要:针对现有符号定时恢复实现算法难以兼顾大吞吐量、高收敛精度和强抗定时误差算法能力的问题,提出一种联合重采样的高速并行定时恢复算法,利用双反馈环实现定时频偏和定时相偏的纠正。在设计并行重采样时,提出并行数控振荡器的实现方式以及利用使能排序和移位寄存器的方式来实现数据重排序。在进行定时恢复环路设计时,分析并推导O&M定时误差估计算法的并行实现结构,在对定时相/频偏纠正原理分析的基础上提出环路纠正的设计方法和实现结构。FPGA实测结果表明,所提算法能够实现最高64APSK调制信号4~16倍任意倍符号率的符号定时恢复,且与理想信号的误差向量幅度(EVM)在4%以内,满足宽带卫星通信需求。Aiming at the problem that it is difficult for existing implementation algorithms of symbol timing recovery to give full consideration to high convergence accuracy and the robustness to resist timing deviation,a high-speed parallel symbol timing recovery algorithm with resampling was proposed.The timing frequency offset and timing phase offset were corrected by using double feedback loops.In the design of parallel resampling,the implementation of parallel numerically controlled oscillators and the use of enable signals sorting and shift registers to implement data reordering were proposed.When designing the timing recovery loop,the parallel implementation structure of the O&M timing error estimation algorithm was analyzed and deduced,and the design method and implementation structure of the loop correction were proposed based on the analysis of the timing phase/frequency offset correction principle.The FPGA test results show that the proposed algorithm can realize the symbol timing recovery of 64APSK modulated signals with arbitrary multiple symbol rate between 4 and 16 times,and the error vector magnitude(EVM)with the ideal signal is within 4%,which meets the requirements of broadband satellite communication.
分 类 号:TN911.7[电子电信—通信与信息系统]
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