基于FPGA的网络数据动态采集系统设计  

Design of a Dynamic Network Data Acquisition System Based on FPGA

作　　者：贺鹏飞[1] HE Peng-fei(Taiyuan City Vocational College,Taiyuan 030027,Shanxi)

机构地区：[1]太原城市职业技术学院,山西太原030027

出　　处：《电脑与电信》2023年第1期101-104,共4页Computer & Telecommunication

摘　　要：为解决数据采集系统数据处理速度慢、数据采集量较小、空间拓展有限的问题,基于FPGA设计一款网络数据动态采集系统,利用Altera DDR3控制器IP核、USB3.0接口芯片控制以及ADC转换芯片AD9237构建系统硬件,并完成基础连接,将数据采集精度维持在12位,数据总线最高可变化成128位宽,经过直流和交流信号时,完成数据并行串联采集,采集效率高。经实验证明,该系统能保证数据动态采集的实时性和准确性,采集精度高,普适性强。In order to solve the problems of slow data processing speed,small data acquisition and limited space expansion in data acquisition system,this paper designs a dynamic data acquisition system based on FPGA,using Altera DDR3 controller IP core,USB3.0 interface chip control and ADC conversion chip AD9237 to build the system hardware,and completes the basic connection.The data acquisition accuracy is maintained at 12bit,and the width of data bus is 128 bit.After DC and AC signal,the data parallel series acquisition is completed,which has high acquisition efficiency.The experiment proves that the system can ensure the real-time and accuracy of dynamic data acquisition,with high accuracy and strong universality.

关 键 词：网络数据采集 采集系统设计 可编程逻辑器 

分 类 号：TP335[自动化与计算机技术—计算机系统结构]