一种两步式斜坡ADC非理想特性分析及设计  

Analysis of non-ideal characteristics and design of two-step slope ADC

作　　者：佟星元[1] 王杨 TONG Xingyuan;WANG Yang(Shaanxi Provincial Research Center for Telecommunication ASIC Design,Xi’an University of Posts and Telecommunications,Xi’an 710121,China)

机构地区：[1]西安邮电大学、陕西省通信专用集成电路设计工程技术研究中心,陕西西安710121

出　　处：《西安邮电大学学报》2022年第6期7-13,共7页Journal of Xi’an University of Posts and Telecommunications

基　　金：国家自然科学基金项目(62271389);陕西省重点科研计划项目(22JY058)。

摘　　要：为了减小两步式斜坡(Two-step Single Slope, TS-SS)模数转换器(Analog-to-Digital Converter, ADC)中寄生电容导致的误差电压,提出了一种两步式斜坡ADC非理想特性分析及设计方法。分析了保持电路非理想特性对整体TS-SS ADC性能的影响,并针对粗细量化衔接处开关的寄生对ADC有效位数的影响,提出采用栅压自举开关来代替金属氧化物半导体型(Metal Oxide Semiconductor, MOS)开关。基于0.18μm互补金属氧化物半导体型(Complementary Metal Oxide Semiconductor, CMOS)工艺,设计了一种由6位粗量化与6位细量化相结合实现的12位TS-SS ADC。仿真结果表明,在40 kS/s采样频率下,ADC的无杂散动态范围为74.62 dB,信噪失真比为68.16 dB。提出的方法可有效降低寄生电容带来的误差电压对ADC有效位数的影响。In order to reduce the voltage error caused by the parasitic capacitance in two-step single slope(TS-SS)analog-to-digital converter(ADC),an analysis of non-ideal characteristics and design method of two-step slope ADC is proposed.The impact of non-ideal characteristics of hold circuit on the overall performance is analyzed for TS-SS ADC.Considering effectiveness that the parasitic capacitance of switch used to connect the coarse and fine quantization circuits has on the number of bits of ADC,a bootstrapped switch is proposed to replace the metal oxide semiconductor(MOS)switch.By using 0.18μm CMOS technology,a 12-bit TS-SS ADC is designed with a combination architecture of 6 coarse quantization bits and 6 fine quantization bits architecture.The simulation results show that the spurious-free dynamic range of the ADC is 74.62 dB,and the signal-to-noise distortion ratio is 68.16 dB at 40 kS/s sampling frequency.The proposed method can effectively reduce the impact of voltage error caused by parasitic capacitance on the ADC effective number of bits.

关 键 词：模数转换器 两步式 斜坡ADC 寄生电容 栅压自举开关 

分 类 号：TN432[电子电信—微电子学与固体电子学]