基于FPGA的多通道高速数据采集系统设计  

Design of Multi-channel High-speed Data Acquisition System based on FPGA

作　　者：李明华 李学华[1] 李镇江 邱国星 LI Minghua;LI Xuehua;LI Zhenjiang;QIU Guoxing(College of Electronic Engineering,Chengdu University of Information Technology,Chengdu 610225,China;CETC10,Chengdu 610036,China)

机构地区：[1]成都信息工程大学电子工程学院,四川成都610225 [2]中国电子科技集团有限公司第十研究所,四川成都610036

出　　处：《成都信息工程大学学报》2023年第2期136-141,共6页Journal of Chengdu University of Information Technology

基　　金：国家自然科学基金资助项目(41575022);四川省自然科学基金资助项目(2022NSFSC0214)。

摘　　要：为满足宽带中频接收机能实现多通道、高速同步采集的需求,提出一种基于FPGA的多通道高速数据采集系统设计方案。系统采用Vertix7系列FPGA芯片作为主控芯片,通过SPI接口同时对4片宽带中频接收器AD6674进行控制,实现8路模拟信号的采集,并通过JESD204B协议完成8路数据的实时接收;AD输入前端采用无源的方式,将模拟输入的单端信号转成差分信号,抑制无用的宽带噪声。系统中采用时钟同步芯片AD9549、时钟扇形缓存器ADCLK950等解决系统内部时钟抖动以及多通道同步问题,为保证多通道同步数据的采集传输提供了解决办法。对整个系统进行功能测试,验证了方案的可行性。In order to realize multi-channel and high-speed synchronous acquisition in wideband IF receiver,a design scheme of wideband and high-speed data acquisition system based on JESD204B is proposed.The system adopts Vertix7 series FPGA chip as the main control chip,which can control four wideband intermediate frequency receivers AD6674 at the same time,realize 8 channels of analog signals acquisition,and complete the 8 channels real-time data reception of through the JESD204B protocol;the clock synchronization chip AD9549 and clock sector cache ADCLK950 are used to solve the internal clock jitter and synchronization problems in the system,and provide solutions for ensuring the acquisition and transmission of multi-channel synchronous data.The whole system is functionally tested to verify the feasibility of the scheme.

关 键 词：宽带A/D JESD204B 多通道 时钟同步 

分 类 号：TN432[电子电信—微电子学与固体电子学]