片上网络容错路由器设计  

Design Fault-tolerant Router for Network-on-Chip

作　　者：聂呈屹 王琴[2] 杨志[1,2] Nie Chengyi;Wang Qin;Yang Zhi(Key Laboratory of Thin Film and Microfabrication(Ministry of Education),Shanghai Jiao Tong University,Shanghai,China;School of Electronic Information and Electrical Engineering,Shanghai Jiao Tong University,Shanghai,China)

机构地区：[1]上海交通大学薄膜与微细技术教育部重点实验室,上海 [2]上海交通大学电子信息与电气工程学院,上海

出　　处：《科学技术创新》2023年第12期47-50,共4页Scientific and Technological Innovation

摘　　要：随着集成电路系统对高带宽、低功耗以及高可拓展性等性能需求的增加,片上网络(NoC)已成为备受关注的高性能、高扩展性互连架构。然而,由于晶体管尺寸的不断缩小,片上网络路由器容易出现故障,导致整个芯片通信中断。因此,需要进行有效的故障容错设计。提出了一种新型容错路由器结构,采用分组共享和辅助路径等技术来实现路由器单元的容错设计。与基准路由器相比,容错面积开销仅为其面积的27.2%,而平均故障时间提升了20.7%,与先进容错路由器Defender相比,能容忍更多的故障数量,路由器硅保护系数提升了7.0%,增强了路由器的可靠性。With the development of integrated circuits,Network-on-Chip(NoC)has received widespread attention as an interconnect architecture with high performance and scalability.However,due to the continuous reduction in transistor size,Network-on-Chip routers are prone to fault,causing interruptions in communication across the entire chip.Therefore,effective fault-tolerant design is necessary.Presents a fault-tolerant router structure for Network-on-Chip,which uses techniques such as packet sharing and auxiliary paths to provide fault-tolerant design for router units.Compared with the baseline router,the fault-tolerant area overhead is only 27.2%of baseline router's area,while increases the Mean Time to Failure(MTTF)by 20.7%.Compared with the advanced fault-tolerant router Defender,it can tolerate more faults,increases the SPF by 7.0%.This enhances the reliability of the router.

关 键 词：片上网络 路由器 故障容错 可靠性 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]