基于比较器的四值电流型CMOS加减电路设计  

Design of Quaternary Logic Current Mode CMOS Add-subtract Circuit Based on Comparator

作　　者：姚茂群[1] 刘志强 YAO Maoqun;LIU Zhiqiang(School of Information Science and Technology,Hangzhou Normal University,Hangzhou 311121,China)

机构地区：[1]杭州师范大学信息科学与技术学院,杭州311121

出　　处：《电子与信息学报》2023年第5期1852-1858,共7页Journal of Electronics & Information Technology

基　　金：国家自然科学基金(61771179)。

摘　　要：该文通过对电流型CMOS电路的阈值控制引入了多值电流型比较器。与2值逻辑电路相比,多值逻辑电路的单条导线允许更多的信息传输。相较于电压信号,电流信号易实现加、减等算术运算,在多值逻辑的设计上更加方便。同时提出了基于比较器的4值基本单元设计方法,实现了4值取大、取小以及反向器的设计,在此基础上设计实现了加法器和减法器。该设计方法在2值、3值以及n值逻辑上同样适用。实验结果表明所设计的电路具有正确的逻辑功能,较之相关文献电流型CMOS全加器有更低的功耗和更少的晶体管数。A multiple valued current mode comparator is introduced to control the threshold of current mode CMOS circuits.Compared with binary logic circuits,a single wire of multiple valued logic circuits allows more information transmission.Compared with voltage signal,current signal is easy to realize arithmetic operations,such as addition and subtraction,which is more convenient in the design of multiple valued logic.At the same time,the design method of quaternary valued basic unit based on comparator is proposed,and the designs of quaternary valued max,min and inverter are realized.On this basis,full adder and subtractor are designed and realized.The design method is also applicable to binary,ternary and n-valued logic.The experimental results show that the designed circuit has correct logic function,lower power consumption and fewer transistors than the current mode CMOS full adder in the relevant literature.

关 键 词：CMOS 多值逻辑 电流型 比较器 

分 类 号：TN432[电子电信—微电子学与固体电子学]