Dynamic power-gating for leakage power reduction in FPGAs  

作　　者：Hadi JAHANIRAD 

机构地区：[1]Department of Electronics and Communication Engineering,University of Kurdistan,Sanandaj 66177-15175,Iran

出　　处：《Frontiers of Information Technology & Electronic Engineering》2023年第4期582-598,共17页信息与电子工程前沿（英文版）

摘　　要：Field programmable gate array (FPGA) devices have become widespread in electronic systems due to their low design costs and reconfigurability.In battery-restricted applications such as handheld electronics systems,low-power FPGAs are in great demand.Leakage power almost equals dynamic power in modern integrated circuit technologies,so the reduction of leakage power leads to significant energy savings.We propose a power-efficient architecture for static random access memory(SRAM) based FPGAs,in which two modes (active mode and sleep mode) are defined for each module.In sleep mode,ultralow leakage power is consumed by the module.The module mode changes dynamically from sleep mode to active mode when module outputs evaluate for new input vectors.After producing the correct outputs,the module returns to sleep mode.The proposed circuit design reduces the leakage power consumption in both active and sleep modes.The proposed low-leakage FPGA architecture is compared with state-of-the-art architectures by implementing Microelectronics Center of North Carolina(MCNC) benchmark circuits on FPGA-SPICE software.Simulation results show an approximately 95%reduction in leakage power consumption in sleep mode.Moreover,the total power consumption (leakage+dynamic power consumption) is reduced by more than 15%compared with that of the best previous design.The average area overhead (4.26%) is less than those of other powergating designs.

关 键 词：Field programmable gate array(FPGA) Leakage power Power-gating Transistor-level circuit design 

分 类 号：TN791[电子电信—电路与系统]