一种动态自偏置的低功耗无片外电容LDO  

A dynamic self⁃biasing low⁃power consumption LDO without extra capacitance outside chip

作　　者：王梓淇 黄少卿 肖培磊[1] 雷晓 WANG Ziqi;HUANG Shaoqing;XIAO Peilei;LEI Xiao(The N0.58 Research Institute of China Electronic Technology Group Corporation,Wuxi 214000,China)

机构地区：[1]中国电子科技集团第五十八研究所,江苏无锡214000

出　　处：《现代电子技术》2023年第11期175-180,共6页Modern Electronics Technique

摘　　要：基于0.13μm工艺设计的低功耗无片外电容LDO,文中采用动态自偏置技术使电路根据负载变化,提供不同的偏置电流,实现两级和三级结构下相互转化。电路采用Cascode Miller补偿,实现高稳定性。输出端加入过冲抑制电路,优化瞬态响应。仿真得到压差电压为57 mV;在-55~125℃范围内,温漂系数为27 ppm/℃;在电源电压1.2~3.3 V和负载100 nA~50 mA的变化范围内,线性调整率为0.452 mV/V,负载调整率为0.074 mV/mA。满载50 mA和电源电压1.2 V时,电源抑制比-53 dB@100 kHz,环路相位裕度大于60°。负载100 nA时静态电流2.5μA。负载瞬态响应结果展示过冲电压小于50 mV,建立时间约420 ns。此电路可调节性强,作为低功耗芯片,有着优秀的稳定性,适用于便携式产品。A low power LDO without extra capacitance outside chip is designed based on 0.13 um technology.The dynamic self⁃biasing technique is used to make the circuit provide the bias current according to the change of load,so as to realize the mutual transformation in the situation of two⁃stage and three⁃stage structures.The Cascode Miller compensation is used in the circuit to achieve high stability.An overshoot rudection circuit is added to the output end of LDO to optimize the transient response.The dropout voltage of 57 mV is obtained by simulation.In the range of-55~125℃,the temperature drift coefficient is 27 ppm/℃.Within the range of 1.2~3.3 V power supply voltage and 100 nA~50 mA load,the linear adjustment rate is 0.452 mV/V and the load adjustment rate is 0.074 mV/mA.When the load is 50 mA and the supply voltage is 1.2 V,the PSRR is-53 dB@100 kHz and the loop phase margin is greater than 60°.The quiescent current is 2.5μA when a load is 100 nA.The load transient response results show that the overshoot voltage is less than 50 mV,and the establishment time is about 420 ns.The LDO circuit is highly adjustable.As a low⁃power chip,it has excellent stability and is suitable for portable products.

关 键 词：低功耗LDO 过冲抑制电路 动态自偏置 瞬态响应 压差电压 结构转换 

分 类 号：TN402-34[电子电信—微电子学与固体电子学]