基于FPGA的数字滤波器设计  

Design of Digital Filter Based on FPGA

作　　者：周钧 樊闯 ZHOU Jun;FAN Chuang(CRRC Dalian Electric Traction Research and Development Center Co.,Ltd.,Dalian Liaoning 116000)

机构地区：[1]中车大连电力牵引研发中心有限公司,辽宁大连116000

出　　处：《中国科技纵横》2023年第7期33-35,共3页China Science & Technology Overview

摘　　要：本文主要对一种基于FPGA技术的数字锁相滤波器的设计。结合Xilinx开发平台,根据噪声信号非时间相干特性进行数字滤波器设计,在SPARTAN-3E硬件板上完成了硬件协同仿真测试,同时给出测试结果。测试结果表明,该数滤波器的消除噪声满足技术要求。This paper focuses on the design of a digital phase-locked filter based on FPGA technology.Combined with Xilinx development platform,the digital filter is designed according to the non temporal coherence of the noise signal,the hardware co simulation test was completed on the SPARTAN-3E hardware board,the test results are also given.The test results show that,the noise elimination of the digital filter meets the technical requirements.

关 键 词：FPGA 非时间相干特性 数字滤波 

分 类 号：TN713.7[电子电信—电路与系统]