一种高分辨率面阵CCD驱动及采集电路设计  

Design of the Driving and Acquisition Circuit for High-Resolution Area Array CCD

作　　者：李志勇 LI Zhiyong(School of Information Engineering,Suzhou University,Suzhou Anhui 234000,China)

机构地区：[1]宿州学院信息工程学院,安徽宿州234000

出　　处：《电子器件》2023年第2期309-313,共5页Chinese Journal of Electron Devices

摘　　要：针对高分辨率面阵CCD驱动及采集需求,研制了一种以双AD9920与FPGA为核心的CCD驱动及采集电路单元、利用AD9920硬件特性,设计了树状层次的驱动时序结构,将时序分为模式、场、垂直序列、垂直图样组四种层次。通过FPGA对各时序层次的动态组合和参数控制,建立了高内聚、低耦合的驱动时序模块,产生了精确同步的6路CCD驱动信号,实现了高分辨率图像的双通道A/D采集。通过可见光CCD成像实验表明,设计的电路达到了主要技术指标:图像分辨率为7326×5494,采集时间为1.3 s/帧,动态范围达到65.7 d B。A CCD driving and acquisition circuit unit based on dual AD9920 and FPGA is developed to meet the requirements of high resolution area array CCD driving and acquisition.A tree-level drive timing structure is designed with the hardware characteristics of AD9920,and the timing sequence is divided into four levels,including mode,field,vertical sequence and vertical pattern group.The high-cohesion and low-coupling driving timing module is set up through the flexible combination and parameter control of each time se-quence level by FPGA,6-channel CCD driving signals with precise synchronization are generated,and the dual-channel A/D acquisition of high-resolution image is realized.The visible light CCD imaging experiments show that the main technical indicators are achieved:the image resolution is 7326×5494,the acquisition time is 1.3 seconds/frame,and the dynamic range is 65.7 dB.

关 键 词：高分辨率 CCD 驱动时序 AD9920 FPGA 

分 类 号：TN386.5[电子电信—物理电子学]