nPSA:一种面向TSN芯片的低延时确定性交换架构  

nPSA:A Low-Latency,Deterministic Switching Architecture for TSN Chips

作　　者：付文文 刘汝霖[1] 全巍[1] 姜旭艳 孙志刚[1,2] Fu Wenwen;Liu Rulin;Quan Wei;Jiang Xuyan;Sun Zhigang(College of Computer Science and Technology,National University of Defense Technology,Changsha 410073;Science and Technology on Parallel and Distributed Processing Laboratory(National University of Defense Technology),Changsha 410073)

机构地区：[1]国防科技大学计算机学院,长沙410073 [2]并行与分布处理国防科技重点实验室(国防科技大学),长沙410073

出　　处：《计算机研究与发展》2023年第6期1322-1336,共15页Journal of Computer Research and Development

摘　　要：时间敏感网络(time-sensitive networking,TSN)通过时空资源规划保证关键流量传输的实时性和确定性,规划工具在分配时间资源时使用关键帧,在重负载情况下进出芯片的最大交换延时时作为输入参数.为了满足TSN应用的低传输延时要求,TSN芯片设计时需要以最小化最大交换延时为重要目标.当前商用TSN芯片一般采用单流水线交换架构,容易在流水线的入口处发生“完整帧阻塞”问题,导致芯片的最大交换延时难以降低.针对此问题,提出了一种基于时分复用的多流水线交换架构(n-pipeline switching architecture,nPSA)该架构将“完整帧阻塞”问题优化成“切片阻塞”问题.同时,提出了面向时分复用机制的加权轮询式时隙分配算法(WRRSA)以求解不同端口类型组合下的时隙分配方案.目前nPSA架构和WRRSA算法已经在OpenTSN开源芯片和“枫林一号”ASIC芯片(HX-DS09)中得到应用.实际测试结果显示,长度为64 B的关键帧在OpenTSN芯片和“枫林一号”芯片中经历的最大交换延时分别为1648 ns和698 ns,与基于单流水线架构的TSN交换芯片的理论值相比,延时数值分别降低约88%和95%.Time-sensitive networking(TSN)guarantees the real-time and determinism for critical traffic through spatio-temporal resource planning.The planning tool uses the maximum switching delay of each chip under heavy load as input parameters when allocating temporal resources.In order to satisfy the low-delay requirement of TSN applications,the TSN chip designers are supposed to minimize the maximum switching delay as an important goal.Current commercial TSN chips generally adopt a single-pipeline switching architecture,which is prone to“complete frame blocking”at the entrance of the pipeline,resulting that it is hard to reduce the maximum switching delay.Therefore,we propose a multi-pipeline switching architecture named nPSA based on time division multiplexing mechanism,which optimizes the“complete frame blocking”into a“slice blocking”problem.Moreover,the weighted round-robin slot allocation algorithm(WRRSA)is proposed for the time division multiplexing mechanism to calculate the slot allocation scheme under different port types.At present,the nPSA architecture and WRRSA algorithm have been applied in the OpenTSN open-source chip and the“HX-DS09”ASIC chip.The actual test results show that the maximum switching delay time experienced by the 64B critical frame in the OpenTSN chip and the“HX-DS09”chip are 1648ns and 698ns,respectively.Compared with the theoretical value are the TSN switching chip designed based on the single-pipeline architecture,the delay value are reduced by about 88%and 95%respectively.

关 键 词：时间敏感网络 交换架构 最大交换延时 时分复用 多流水线 时隙分配算法 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]