粘接层空洞对功率芯片热阻的影响  

Influence of Bonded Layer Cavity on Power Chip

作　　者：潘浩东 卢桃 陈晓东 何骁[1] 邹雅冰[1] PAN Haodong;LU Tao;CHEN Xiaodong;HE Xiao;ZOU Yabin(The 5th Research Institute of MII,Guangzhou 511370,China)

机构地区：[1]工业和信息化部电子第五研究所,广州511370

出　　处：《电子工艺技术》2023年第3期13-16,20,共5页Electronics Process Technology

基　　金：广东省基础与应用研究基金项目(2022A1515110385)。

摘　　要：采用有限元数值模拟方法,建立金氧半场效晶体管(MOSFET)三维有限元模型,定义不同大小和位置的粘接层空洞模型,对器件通电状态下的温度场进行计算,讨论空洞对于热阻的影响。有限元仿真结果表明,随着芯片粘接层空洞越大,器件热阻随之增大,在低空洞率下,热阻增加缓慢,高空洞率下,热阻增加更明显;总空洞率一致时,不同位置空洞对应器件热阻的关系为中心空洞>拐角空洞>阵列空洞。采用双界面法对含有空洞缺陷的器件进行了热阻测试,将试验数据修正仿真结果,获得准确的空洞-热阻曲线,对于芯片粘接空洞工艺控制提供理论参考。A three-dimensional finite element model of MOSFET is established by the finite element numerical simulation method.The cavity models of different sizes and positions of the bonding layer are defi ned.The temperature fi eld of the device under the current state is calculated,and the infl uence of the cavity on the thermal resistance is discussed.The finite element simulation results show that the thermal resistance of the device increases with the increase of the hole in the chip bonding layer,the thermal resistance increases slowly at the low cavity rate and more obviously at the high cavity rate,and when the total cavity rate is the same,the corresponding thermal resistance of the device at different positions is center cavity>corner cavity>array cavity.The dual-interface method is also used to test the thermal resistance of the device with cavity defects,and the experimental data is modifi ed to obtain the accurate cavity thermal resistance curve,which provides a theoretical reference for the chip bonding cavity process control.

关 键 词：粘接空洞 温度分布 热阻 数值模拟 

分 类 号：TN405[电子电信—微电子学与固体电子学]