基于FPGA的CAVLC并行编码设计  

Design of CAVLC Parallel Coding Based on FPGA

作　　者：罗超[1] LUO Chao(Jiangsu Institute of Automation,Lianyungang,Jiangsu 222000,China)

机构地区：[1]江苏自动化研究所,江苏连云港222000

出　　处：《自动化应用》2023年第8期213-217,共5页Automation Application

摘　　要：除拖尾系数外的非零系数幅值的编码过程是CAVLC编码过程中计算量最大、复杂度最高、编码延时最长的部分,且无法利用大规模的并行处理来缩短时钟周期数,一定程度地造成了编码瓶颈。本文优化了串行实现方法,设计了一种基于三级流水线和并行处理相结合的双路并行幅值编码器,节省了时钟周期数,并能提供稳定的数据吞吐率。优化编码查表法,减少存储资源消耗,有效提高了工作频率。In the process of CAVLC coding,the encoding of on-zero coefficient amplitude,except for trailing coefficients,requires the highest amount of computation,rendering it the most complex and time-consuming part of the coding process.Moreover,the limitation of larger-scale parallel processing has resulted in encoding bottlenecks.To address this issue,this study proposes an optimized serial implementation method and dual-channel parallel amplitude encoder that deploys a combination of three-stage pipeline and parallel processing,thereby reducing the number of clock cycles and enabling stable data throughput.Furthermore,the study optimizes the code look-up table method,reducing storage resource consumption,and improving the working frequency.

关 键 词：CAVLC 三级流水线 并行编码 查找表 FPGA 

分 类 号：TP277[自动化与计算机技术—检测技术与自动化装置]