一种并行信号多核DSP的块数据处理和传输方法  

Block Data Processing and Transmission Method of Parallel Signal Muti-core DSP

作　　者：唐宇[1] Tang Yu(The 10th Research Institute of China Electronics Technology Corporation,Chengdu 610036,China)

机构地区：[1]中国电子科技集团公司第十研究所,成都610036

出　　处：《单片机与嵌入式系统应用》2023年第6期17-19,共3页Microcontrollers & Embedded Systems

摘　　要：针对并行信号处理和传输资源消耗大的问题,利用高速RapidIO总线将多核DSP全互连,数据通过内存映射共享,8个核可分别并行传输和处理数据,轻量级包头的RapidIO块传输速率高、复制数据少、效率高。经验证大大提高了数据吞吐率、减少了传输时延,解决了传统FPGA器件实现并行计算编译时间长、调试困难、价格昂贵等问题,可推广到雷达信号脉冲压缩、SAR图像处理、分布式智能云计算等领域。Aiming at the problem of parallel signal processing and large consumption of transmission resources,the high-speed RapidIO bus is used to fully interconnect multi-core DSP,and the data is shared through memory mapping.Eight cores can transmit and process data in parallel respectively.The RapidIO block with lightweight header has high transmission rate,few data copies and high efficiency.It has been proved that the data throughput has been greatly improved,the transmission delay has been reduced,and the problems such as long compilation time,difficult debugging,and high price in parallel computing of traditional FPGA devices have been solved.It can be extended to radar signal pulse compression,SAR image processing,distributed intelligent cloud computing and other fields.

关 键 词：TMS320C6678 全互连 内存映射 并行计算 RAPIDIO 

分 类 号：TN919[电子电信—通信与信息系统]