基于可编程逻辑门阵列软硬件协同设计的心律失常分类系统  

An Electrocardiogram Arrhythmia Classification System Based on Software Hardware Co-design with Field Programmable Gate Array

作　　者：康磊[1] 任旭超 陈宇骞 梅海红 颜延[2] KANG Lei;REN Xuchao;CHEN Yuqian;MEI Haihong;YAN Yan(College of Computer Science,Xi’an Shiyou University,Xi’an 710065,China;Shenzhen Institute of Advanced Technology,Chinese Academy of Sciences,Shenzhen 518055,China;Faculty of Intelligent Manufacturing,Wuyi University,Jiangmen 529000,China)

机构地区：[1]西安石油大学计算机学院,西安710065 [2]中国科学院深圳先进技术研究院,深圳518055 [3]五邑大学智能制造学部,江门529000

出　　处：《集成技术》2023年第3期82-93,共12页Journal of Integration Technology

基　　金：国家重点研发计划项目(2020YFC2007203)。

摘　　要：近年来,心律失常分类成为生理信号分析中的研究热点。心律失常现象在临床上十分常见,其出现时伴随心电信号中的心拍呈现具有反常形态和节律的波形。正确及时地检测、发现心律失常,并准确地进行心血管疾病的预警,在临床诊断初期具有重要意义。但人工判断异常心电图的远程系统实时性较低,可能延误病人的最佳治疗时机。将心律失常分类算法应用在可穿戴设备等边缘侧智能终端,一方面能够对心电信号进行实时分析处理,另一方面也提高了设备的灵活性及安全性。可编程逻辑门阵列器件作为边缘计算的一种实现形式,在生理信号处理中已经得到了广泛的应用,虽然可编程逻辑门阵列可进行实时流水线操作,但其基于Verilog或VHDL硬件描述语言,具有开发周期长、成本高、难度大及调试困难等缺点。针对这一问题,该文采用Xilinx公司新推出的高层次综合工具Vivado HLS,以实现基于MIT-BIH数据集的心律失常五分类算法,并使用Xilinx Zynq FPGA作为硬件平台,在心电信号测试集上进行测试。测试结果显示,该系统的平均分类准确率可达99.12%,单个心拍分类平均耗时3.185 ms,与纯PS端的单ARM核相比,该系统实现了5.64倍以上的加速性能。Arrhythmia classification is a hot topic in physiological signal analysis.Arrhythmias are very common in clinical practice,and they are accompanied by abnormal patterns and rhythms in the heartbeat of the electrocardiogram signal.Correct and timely detection of arrhythmias and accurate early warning of cardiovascular diseases are of particular importance in the early stage of clinical diagnosis.However,the lack of real time diagnosis of electrocardiogram may delay the best time for patient treatment.Implementing heart rate disorder classification algorithms at edge-side smart terminals such as wearable devices enable real-time analysis and processing of electrocardiogram signals.In addition,they improve the flexibility and safety of the devices as well.By far,the field programmable gate array devices have been widely used in physiological signal processing as a form of edge computing due to its capability of real-time pipeline operation.Whereas,the field programmable gate array implementation needs a long development cycle,has high cost and is difficult to debug.To address these problems,the new high-level synthesis tool Vivado HLS from Xilinx is used to implement the arrhythmia five classification algorithm based on the MIT-BIH dataset.By using a Xilinx Zynq field programmable gate array,an average classification accuracy of 99.12%on the electrocardiogram signal test set is achieved.Moreover,an average of 3.185 ms required to classify a single heartbeat is realized,which leads to a speedup of more than 5.64 times compared to a single ARM core on the pure PS side.

关 键 词：心电图 心律失常分类 Vivado HLS Zynq嵌入式系统 

分 类 号：TP391.4[自动化与计算机技术—计算机应用技术]