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作 者:王鑫[1] 陈博 WANG Xin;CHEN Bo(School of Internet of Things Engineering,Jiangnan University,Wuxi 214122,China)
机构地区:[1]江南大学物联网工程学院,江苏无锡214122
出 处:《计算机测量与控制》2023年第6期293-298,共6页Computer Measurement &Control
基 金:国家自然科学基金(61703185);高等学校学科创新引智计划项目(B12018)。
摘 要:针对卷积神经网络加速器中有关于脉动阵列模块的验证,提出并实现了一种基于直接编程接口C(DPI-C)程序的验证平台,采用内嵌DPI-C程序并利用通用验证方法学(UVM)满足脉动阵列模块中的浮点数乘加运算的验证需求;实验利用了SystemVerilog中的DPI接口技术,在验证平台中实现对C或C++代码的调用,通过编写C函数来实现复杂的参考模型,浮点数乘加运算便是利用C代码编写的;验证平台的整体结构是根据UVM来设计的,其中包括激励的设计、参考模型的编写、数据校对等组件,整个验证平台高效、简洁;此平台已经应用于人工智能芯片的验证工作中,编写的测试用例可以对脉动阵列进行充分验证,覆盖率达到了100%;验证平台可以保证脉动阵列验证的全面性、高效性并且调试纠错简单方便,同时还实现了UVM环境和测试用例的重用。Aiming at the verification of a systolic array module in convolutional neural network accelerator,a verification platform based on the direct programming interface C(DPI-C)program is proposed and implemented.The embedded DPI-C program and universal verification methodology(UVM)are used to meet the verification requirements of floating-point multiplication and addition in the systolic array module.In the experiments,the DPI interface technology in SystemVerilog is used to implement calls to C or C++code in the verification platform.Complex reference models are implemented by writing C functions,and floating-point multiplication and addition operations are written by using C code.The overall structure of the verification platform is designed by the UVM,which includes the excitation design,reference model writing,data proofreading and other components,and the whole verification platform is efficient and concise.The platform is already applied in the verification of artificial intelligence chip,and the written test examples can fully verify the systolic arrays with 100%coverage.The verification platform ensures the comprehensive and efficient verification of systolic arrays and easy debugging and error correction,and realizes the reuse of the UVM environment and test examples.
关 键 词:直接编程接口C 验证平台 验证方法学 脉动阵列 人工智能芯片
分 类 号:TP391.9[自动化与计算机技术—计算机应用技术]
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