多级缓存数据预取处理器访存性能测试方法  

Testing Methods for Memory Access Performance of Multi-level Cache Data Prefetching Processor

作　　者：钟伟军 田晨燕[1] 

机构地区：[1]中国电子技术标准化研究院

出　　处：《信息技术与标准化》2023年第6期25-29,共5页Information Technology & Standardization

摘　　要：针对处理器内存访问性能测试缺少对多级缓存数据预取优化而导致测试数据不能真实反映实际性能的问题,分析了多级缓存数据预取优化技术及其对内存访问带宽的影响。提出了一种针对多级缓存处理器的访存性能优化测试方法,该方法充分利用缓存数据预取机制,并避免处理器核间资源竞争,实现访存性能提升。实验数据表明,采用该方法可以得到符合硬件实际访存性能的数据,为准确评估高性能处理器的访存能力提供支持。In response to the issue of lack of optimization for multi-level cache data prefetching in processor memory access performance testing,which often results in test data not reflecting actual performance,this paper analyzes the optimization technology for multi-level cache data prefetching and its impact on memory access bandwidth.A memory access performance optimization testing method for multi-level cache processors is proposed,which fully utilizes the cache data prefetching mechanism and avoids resource competition between processor cores,achieving improved memory access performance.Experimental verification was conducted,and the experimental data showed that using this method can obtain data that matches the actual memory access performance of hardware,providing support for accurately evaluating the memory access capability of high-performance processors.

关 键 词：多级缓存 缓存数据预取 访存性能 处理器 访存带宽 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]