相控-延时链混合架构时间数字转换器  

Hybrid architecture time to digital converter with phased clocks-delay chains

作　　者：李国梁 韩斌 程阳[1,2] 曹杰[1,2] 鲍春 吴昊泽 LI Guoliang;HAN Bin;CHENG Yang;CAO Jie;BAO Chun;WU Haoze(School of Optics and Photonics,Beijing Institute of Technology,Beijing 100081,China;Yangtze Delta Region Academy of Beijing Institute of Technology,Jiaxing 314003,China)

机构地区：[1]北京理工大学光电学院,北京100081 [2]北京理工大学长三角研究院(嘉兴),浙江嘉兴314003

出　　处：《中国测试》2023年第6期130-136,共7页China Measurement & Test

基　　金：北京市自然科学基金(4222017)。

摘　　要：高精度时间间隔测量过程中,为兼顾测量分辨和精度的同时,简化校准过程,提出一种混合架构的时间数字转换器(TDC)设计方法。该方法将相控时钟架构与抽头延时链(TDL)架构结合,利用不同相位的时钟对抽头延时链实现并行采样,一次测量过程中可以得到多个测量值,最后利用多个测量值的均值表示测量结果。该方法在Kintex-7 FPGA上进行实验测试,结果表明在进行简单校准的情况下,仍然可以保持较高的测量分辨率和精度,从而证明提出方法的有效性与可行性。In the process of high precision time interval measurement,in order to simplify the calibration process without affecting the measurement resolution and accuracy,a hybrid architecture time to digital converter(TDC)design method is proposed.This method combines the phased clock architecture with the tap delay line(TDL)architecture,and the clock with different phases is used to sample the tap delay line in parallel.Multiple measured values can be obtained in a single measurement process,and the mean value of multiple measured values is used to represent the measurement results.The presented method is implemented on a Kintex-7 FPGA,and the results show that the proposed method can still maintain high measurement resolution and accuracy even with simple calibration,which proves the effectiveness and feasibility of the proposed method.

关 键 词：时间数字转换器 FPGA 延时链 相控时钟 

分 类 号：TB9[一般工业技术—计量学]