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作 者:C.Arun Prasath C.Gowri Shankar
机构地区:[1]Department of Electronics and Communication Engineering,Mahendra Engineering College,Namakkal,637503,India [2]Department of Electrical and Electronics Engineering,KSR College of Engineering,Tiruchengode,637215,India
出 处:《Intelligent Automation & Soft Computing》2023年第2期1767-1781,共15页智能自动化与软计算(英文)
摘 要:Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor(CMOS)-based Very Large-Scale Integration(VLSI)circuit designs.Positive Channel Metal Oxide Semiconductor(PMOS)has been replaced by Negative Channel Metal Oxide Semiconductor(NMOS)in recent years,with low dimen-sion-switching changes in order to shape the mirror of voltage comparator.NMOS is used to reduce stacking leakage as well as total exchange.Domino Logic Cir-cuit is a powerful and versatile digital programmer that gained popularity in recent years.In this study regarding Adaptive Sub Threshold Voltage Level Control Pro-blem,the researchers intend to solve the contention issues,reduce power dissipa-tion,and increase the noise immunity by proposing Adaptive Sub Threshold Voltage Level Control(ASVLC)-based domino circuit.The efficiency and effec-tiveness of the domino circuit are demonstrated through simulation results.The suggested system makes use of high-speed broad fan-gate circuits,occupies mini-mum space,and consumes meagre amount of power.The proposed circuit was validated in Cadence simulation tool at a supply voltage of 1V,frequency of 100 MHz,and an operating temperature of 27°C with 64 input OR gates.As per the simulation results,the suggested Domino Gate reduced the power dissipa-tion by 17.58 percent and improved the noise immunity by 1.21 times in compar-ison with standard domino logic circuits.
关 键 词:Domino logic power consumption figure of merit adaptive sub-threshold voltage level wide fan-in gates
分 类 号:TP18[自动化与计算机技术—控制理论与控制工程]
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