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作 者:Zihan XIA Rui WAN Jienan CHEN Runsheng WANG
机构地区:[1]National Key Laboratory of Science and Technology on Communications,University of Electronic Science and Technology of China,Chengdu,611731,China [2]School of Integrated Circuits,Peking University,Beijing,100871,China
出 处:《Science China(Information Sciences)》2023年第6期263-282,共20页中国科学(信息科学)(英文版)
基 金:supported by National Key Research and Development Program (Grant No.2020YFB2205500)。
摘 要:Edge devices play an increasingly important role in the convolutional neural network(CNN)inference.However,the large computation and storage requirements are challenging for resource-and powerconstrained hardware.These limitations might be overcome by exploring the following:(a)error tolerance via approximate computing,such as stochastic computing(SC);(b)data sparsity,including the weight and activation sparsity.Although SC can perform complex calculations with compact and simple arithmetic circuits,traditional SC-based accelerators suffer from the low reconfigurability and long bitstream,further making it difficult to benefit from the data sparsity.In this paper,we propose spatial-parallel stochastic computing(SPSC),which improves the spatial parallelism of the SC-based multiplier to the full extent while consuming fewer logic gates than the fixed-point implementation.Moreover,we present SPA,a highly reconfigurable SPSC-based sparse CNN accelerator with the proposed hybrid zero-skipping scheme(HZSS),to efficiently take advantage of different zero-skipping strategies for different types of layers.Comprehensive experiments show that SPA with up to 2477.6 Gops/W outperforms existing several binary-weight accelerators,SC-based accelerators,and the sparse CNN accelerator considering energy efficiency.
关 键 词:convolutional neural networks stochastic computing sparse neural networks energy-efficient accelerator high reconfigurability spatial parallelism
分 类 号:TP183[自动化与计算机技术—控制理论与控制工程]
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