一种电流失配自适应补偿宽带锁相环设计  

Design of a Broadband PLL with Current Mismatch Adaptive Compensation

作　　者：韦雪明[1] 梁东梅 谢镭僮 尹仁川 李力锋 Wei Xueming;Liang Dongmei;Xie Leitong;Yin Renchuan;Li Lifeng(Guangxi Key Laboratory of Wireless Broadband Communication and Signal Processing,Guilin University of Electronic Science and Technology,Guilin 541004,China;Guangxi University Key Laboratory of Microelectronic Devices and Integrated Circuits,Guilin University of Electronic Science and Technology,Guilin 541004,China)

机构地区：[1]桂林电子科技大学广西无线宽带通信与信号处理重点实验室,广西桂林541004 [2]桂林电子科技大学广西高校微电子器件与集成电路重点实验室,广西桂林541004

出　　处：《半导体技术》2023年第6期500-505,526,共7页Semiconductor Technology

基　　金：国家自然科学基金资助项目(62164003);广西无线宽带通信与信号处理重点实验室主任基金资助项目(GXKL06200131);广西创新研究团队项目(2018GXNSFGA281004);桂林电子科技大学研究生教育创新计划资助项目(2022YCXS034)。

摘　　要：针对宽带自偏置锁相环(PLL)中存在严重的电荷泵电流失配问题,提出了一种电流失配自适应补偿自偏置锁相环。锁相环通过放大并提取参考时钟与反馈时钟的锁定相位误差脉冲,利用误差脉冲作为误差判决电路的控制时钟,通过逐次逼近方法自适应控制补偿电流的大小,逐渐减小鉴相误差,从而减小了锁相环输出时钟信号抖动。锁相环基于40 nm CMOS工艺进行设计,后仿真结果表明,当输出时钟频率为5 GHz时,电荷泵输出噪声从-115.7 dBc/Hz@1 MHz降低至-117.7 dBc/Hz@1 MHz,均方根抖动从4.6 ps降低至1.6 ps,峰峰值抖动从10.3 ps降低至4.7 ps。锁相环输出时钟频率为2~5 GHz时,补偿电路具有良好的补偿效果。For the serious charge pump current mismatch problem in broadband self⁃biased phase⁃locked loop(PLL),a self⁃biased PLL with adaptive compensation for current mismatch was proposed.The PLL amplified and extracted the locked phase error pulse of the reference clock and the feedback clock,used the error pulse as the control clock of the error judgment circuit,and adaptively controlled the compensation current through the successive approximation method to gradually reduce the phase detection error,thereby reducing PLL output clock signal jitter.The PLL was designed based on 40 nm CMOS process.Post simulation results show that when the output clock frequency is 5 GHz,the charge pump output noise is reduced from-115.7 dBc/Hz@1 MHz to-117.7 dBc/Hz@1 MHz,the RMS jitter is reduced from 4.6 ps to 1.6 ps,and the peak⁃to⁃peak jitter is reduced from 10.3 ps to 4.7 ps.The compensation circuit has a good compensation effect when the output clock frequency range of the PLL is 2 GHz to 5 GHz.

关 键 词：电荷泵失配电流 电流补偿 自适应控制 自偏置锁相环(PLL) 抖动 

分 类 号：TN911.8[电子电信—通信与信息系统] TN432[电子电信—信息与通信工程]