类AES算法S盒的优化实现  

Optimized Realization of AES-Like Algorithm S-Box

作　　者：李艳俊 张伟国[2] 葛耀东 黄雅婷 霍珊珊 LI Yan-Jun;ZHANG Wei-Guo;GE Yao-Dong;HUANG Ya-Ting;HUO Shan-Shan(Information Industry Information Security Evaluation Center,The 15th Research Institute of China Electronics Technology Group Corporation,Beijing 100083,China;Beijing Electronic Science and Technology Institute,Beijing 100070,China)

机构地区：[1]中国电子科技集团公司第十五研究所信息产业信息安全测评中心,北京100083 [2]北京电子科技学院,北京100070

出　　处：《密码学报》2023年第3期531-538,共8页Journal of Cryptologic Research

基　　金：北京高校“高精尖”学科建设项目(20210101Z0401);中央高校基本科研业务费(328202238)。

摘　　要：本文基于多项式基构造有限域上运算来优化类AES算法的S盒.通过搜索域间的同构映射矩阵,将GF(28)上有限域求逆运算转换到复合域GF((2^(4))^(2))中.利用SAT求解器搜索简化有限域GF(2^(4))上的乘法逆运算,给出2种不同的多项式基优化方案.方案1使用传统的3类门电路来构建复合域.在方案1的基础上,方案2使用了比特级的优化方法,引入MUX门电路,电路面积和门电路数量比方案1更少.使用SMIC130 nm和SMIC65 nm工艺对电路面积进行评估.在现有使用同种类门电路的方案中,本文的结果较优.Based on a polynomial basis,this paper constructs a finite field operation to optimize the S-box of the AES algorithm.By searching for the isomorphic mapping matrix between the fields,the inverse operation over finite field GF(2^(8))is converted to the composite field GF((2^(4))^(2)).By using the SAT solver to search for the multiplication inverse operation over the finite field GF(2^(4)),two different polynomial basis optimization schemes are proposed.Scheme 1 uses the classic Class 3 gate circuit to construct the composite field.Based on Scheme 1,Scheme 2 uses a bit-level optimization method that introduces a MUX gate,and has less circuit area and smaller number of gates than those in Scheme 1.This paper uses the SMIC130 nm and SMIC65 nm processors to evaluate the circuit area.The evaluation shows that the results of this paper are better than the existing schemes using the same kind of gate circuits.

关 键 词：AES算法 S盒硬件实现 多项式基 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]