基于RISC-V架构的Spike缓存模型的设计和实现  

Design and implementation of Spike cache model based on RISC-V architecture

作　　者：唐屹晨 孙维东 胡小刚 毛晓炜 Tang Yichen;Sun Weidong;Hu Xiaogang;Mao Xiaowei(China Key System&Integrated Circuit Co.,Ltd.,Wuxi 214072,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214072

出　　处：《电子技术应用》2023年第7期48-54,共7页Application of Electronic Technique

摘　　要：使用基于精简指令集原则的指令架构(RISC-V)的指令集,针对现有Spike验证模型中的缓存写回功能的缺失问题,设计一种基于RISC-V指令集的现代超标量处理器缓存模型。基于现代高速缓存的基本原理,结合Spike验证模型,实现现代高速缓存的基本读写操作,并进行系统级芯片(SoC)环境下的仿真和验证,可作为微型电子芯片(IC)前端逻辑设计中的验证模型使用。该方案能够以较快的时间完成基于RISC-V指令集的大型SoC的设计与验证。In order to solve the cache write back missing problem of the Spike verification model,this paper presents a superscalar cache model based on the reduced instruction set computer(RISC-V)instruction set。This cache model is based on the Spike environment,the cache model implements the basic principles of superscalar cache.This cache model implements the high level cache write back and write through process,and it is verified in the system level chip(SoC)simulation.This scheme can be used as a model for front-end logic verification,and it can complete large scale verification based on the RISC-V instruction set in a shorter time.

关 键 词：RISC-V SPIKE 缓存模型 

分 类 号：TN407[电子电信—微电子学与固体电子学]