一种高能效双发射处理器的设计与实现  

Design and Implementation of an Energy Efficient Dual-Issue Processor

作　　者：张馨予 刘亮 王春萌 江凇 易江芳[1] ZHANG Xinyu;LIU Liang;WANG Chunmeng;JIANG Song;YI Jiangfang(Institute of System Architecture,School of Computer Science,Peking University,Beijing 100871;Beijing Smart-Chip Microelectronics Technology Co.,Ltd,Beijing 100192;STAET GRID Jiangsu Electric Power CO.LTD Information&Telecommunication Branch,Nanjing 210000)

机构地区：[1]北京大学计算机学院系统结构研究所,北京100871 [2]北京智芯微电子科技有限公司,100192 [3]国网江苏省电力有限公司信息通信分公司,南京210000

出　　处：《北京大学学报（自然科学版）》2023年第4期555-562,共8页Acta Scientiarum Naturalium Universitatis Pekinensis

基　　金：国家电网总部科技项目(5700-202141449A-0-0-00)资助。

摘　　要：为了提高高能效处理器的性能,基于ECore嵌入式处理器平台,在单反射按序流水线结构中引入两种轻量化的超标量结构——压缩指令双发射结构和选择性重命名结构。在Verilator生成的C++模型上进行的模拟实验结果表明,通过增加压缩指令双发射结构,流水线双发利用率平均值达到28%。通过增加选择性重命名结构,因名称冒险导致的流水线停顿占比从7.2%降至0.6%。相对于优化前,处理器的IPC提升4.8%,而功耗仅增加2.5%。In order to improve performance with stable power consumption,based on ECore embedded processor platform,which had a single-issue in-order pipeline structure originally,two lightweight superscalar structures were introduced:selective register renaming and dual issue of compact instructions.The experimental data showed that the average utilization of dual-issue structure reached 28%by adding dual issue logic.Using selective register renaming,the average stalling rate caused by name hazard reduced from 7.2%to 0.6%.Compared with the original design,the IPC increased 4.8%and the power consumption only increased 2.5%.

关 键 词：高能效处理器 双发射 寄存器重命名 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]