超声波电源中数字鉴相器设计  

Design of digital phase detector in ultrasonic power supply

作　　者：刘宁庄[1] 龙路阳 杜光辉 段富才 LIU Ningzhuang;LONG Luyang;DU Guanghui;DUAN Fucai(School of Electrical and Control Engineering,Xi’an University of Science and Technology,Xi’an 710062,China)

机构地区：[1]西安科技大学电气与控制工程学院,西安710000

出　　处：《应用声学》2023年第4期730-736,共7页Journal of Applied Acoustics

基　　金：国家自然科学基金项目(51807075)。

摘　　要：超声波电源系统中电压电流相位差测量精度影响着换能器振幅稳定性以及系统工作效率。目前基于异或门原理,采用分立数字芯片实现鉴相的方案,存在信号调理电路复杂、线性范围小、精度低等问题。为提高电压电流鉴相精度,该文提出了一种数字鉴相器设计。该数字鉴相器采用正交解调原理鉴相,并使用坐标旋转数字算法在FPGA上实现了鉴相器的设计,简化了电路,减少了杂散信号的干扰。经过Modelsim仿真测试表明在30 dB信噪比条件下鉴相误差为0.21°,最后经过实验测试,数字鉴相器鉴相最大误差绝对值为0:256°,提高了测量精度。The measurement accuracy of the voltage and current phase difference in the ultrasonic power system affects the amplitude stability of the transducer and the working efficiency of the system.At present,based on the principle of XOR gate and using discrete digital chips to realize phase detection,there are problems such as complex signal conditioning circuit,small linear range and low precision.In order to improve the accuracy of voltage and current phase detection,this paper proposes a design of a digital phase detector.The digital phase detector adopts the principle of quadrature demodulation to detect the phase,and uses the coordinate rotation digital computer(CORDIC)algorithm to realize the design of the phase detector on the field programmable gate array(FPGA)which simplifies the circuit and reduces the interference of spurious signals.The Modelsim simulation test shows that the phase detection error under the condition of 30 dB signal-to-noise ratio is 0.21°.Finally,through the physical test,the absolute value of the maximum phase detection error of the digital phase detector is 0.256°,which improves the measurement accuracy.

关 键 词：超声波电源 正交解调 数字鉴相器 坐标旋转数字算法 

分 类 号：TN930[电子电信—信号与信息处理]