一种对小数N分频PLL的自抖动和时钟优化方法  

A Self-dithering and Clock Optimization Method forΔΣFractional-N PLL

作　　者：陈祥雨[1] CHEN Xiangyu(School of Foreign Languages,Southeast University,Nanjing 211189,China)

机构地区：[1]东南大学外国语学院,江苏南京211189

出　　处：《无线电工程》2023年第8期1844-1852,共9页Radio Engineering

基　　金：国家部委基金资助项目。

摘　　要：提出了一种针对小数频率综合器的自抖动和时钟优化方法,该方法可以降低ΔΣ小数N分频锁相环(Phase Locked Loop,PLL)分数杂散,降低其带内相位噪声。小数ΔΣ调制器是一种有限状态机,其输出信号具有不可避免的周期性。因此,需要添加抖动序列以破坏周期性循环。设计了一种自抖动方法,该方法不需要通过外部电路来生成抖动。为了减少PLL的非线性对量化噪声的频谱搬移,利用高频时钟同步技术改善PFD量化效果。整个ΔΣ小数N分频PLL均采用了SMIC 0.18μm的CMOS工艺设计。仿真结果显示,设计的频率综合器覆盖了1.5~2.1 GHz的调节范围,在100 kHz偏移下的相位噪声小于-95 dBc/Hz,在1 MHz偏移下的噪声小于-110 dBc/Hz。在1.8 V的电源电压下,功耗仅为14.4 mW。A self-dithering and clock optimization method is presented that realizes fractional spur canceling and low in-band phase noise inΔΣfractional-N PLL practically used in wireless communication systems.A digital delta-sigma modulator is a finite state machine,and its output is cyclical.Hence,a dither sequence to disrupt periodic cycles is necessary.A self-dithering method is proposed,which does not require external circuit to generate the dither.In order to reduce the nonlinear of PLL,a clock optimization method is adopted.The wholeΔΣfractional-N PLL is designed in SMIC 0.18μm CMOS process.Simulation results show that it covers the tuning range from 1.5 to 2.1 GHz,with phase noise smaller than-95 dBc/Hz at 100 kHz offset,and smaller than-110 dBc/Hz at 1 MHz offset.Its power consumption is only 14.4 mW under 1.8 V supply voltage.

关 键 词：小数N分频PLL ΔΣ调制器 自抖动 时钟优化 低功耗多模分频器 

分 类 号：TN74[电子电信—电路与系统]