一种应用于宽带锁相环的小数分频器  

A Fractional Divider Applied in Wideband Phase-locked Loop

作　　者：范海宇 张国华[1,2] 沈剑 杨俊浩[2] 马瑞山 FAN Haiyu;ZHANG Guohua;SHEN Jian;YANG Junhao;MA Ruishan(School of Internet of Things Engineering,Jiangnan University,Wuri,Jiangsu,214122,CHN;The 58th Research Institute of China Electronics Technology Group Corporation,Wuri,Jiangsu,214035,CHN)

机构地区：[1]江南大学物联网工程学院,江苏无锡214122 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《固体电子学研究与进展》2023年第3期259-265,共7页Research & Progress of SSE

基　　金：国家自然科学基金资助项目(62174149);江苏省自然基金资助项目(BK20211042)。

摘　　要：基于0.13μm SiGe BiCMOS工艺,设计了一款高性能的可编程小数分频器。采用电流模逻辑(Current mode logic,CML)设计了4/5双模分频器和19 bit的可编程计数器,实现了低相噪、宽分频比范围的整数分频。采用多级噪声整形结构Σ-Δ调制器,阶数和模数均可编程,实现了高精度的小数分频值,同时加入随机数生成器,进一步抑制了小数杂散。该小数分频器应用在7.5~15.0 GHz宽带锁相环中,其流片测试结果显示:锁定在15 GHz下的锁相环相位噪声可达-115.34 dBc/Hz@1 MHz,开启四阶调制器和随机抖动,小数杂散可达到-80 dBc以下。Based on 0.13μm SiGe BiCMOS technology,a high performance programmable deci-mal divider was designed.A 4/5 dual-mode frequency divider and a 19 bit programmable counter were designed by using current mode logic(CML)to achieve integer frequency division,with low phase noise and wide frequency division ratio range.TheΣ-△modulator with multilevel noise shaping struc-ture realized high precision fractional frequency division,which was programmable in both order and modulus.Meanwhile,the random number generator was added to further suppress the decimal spuri-ous.Applied in 7.5-15.0 GHz broadband phase-locked loop,after the tape-out test of 0.13μm SiGe BiC-MOS process,the phase noise of the phase-locked loop locked at 15 GHz can reach-115.34 dBc/Hz@1 MHz.When the forth-order modulator and random jitter are enabled,the fractional spur can reach less than-80 dBc.

关 键 词：CML Σ-Δ调制器 小数杂散 相位噪声 

分 类 号：TN772[电子电信—电路与系统]