具有预加重作用的10 Gbps发送端设计  

Circuit Design for 10 Gbps Transmitter Circuit with Pre-Emphasis

作　　者：王雷 刘涛 陈鑫[1] 张颖[1] WANG Lei;LIU Tao;CHEN Xin;ZHANG Ying(College of Electronic Information Engineering,Nanjing University of Aeronautics and Astronautics,Nanjing Jiangsu 211106,China)

机构地区：[1]南京航空航天大学电子信息工程学院,江苏南京211106

出　　处：《电子器件》2023年第3期608-614,共7页Chinese Journal of Electron Devices

基　　金：模拟集成电路重点实验室基金项目(61428020304);国家自然科学基金项目(61106029,61701228);航空科学基金(20180852005)。

摘　　要：针对10 Gbps高速SerDes发送端信号完整性问题,对关键模块进行优化设计,包括高速串行器、前馈均衡电路(FFE)、电流数模转换器(IDAC)控制电路等。为降低时钟性能的要求,对传统电流模逻辑(CML)串行器进行改进,通过调整时钟占空比的方法,设计四分之一速率的串行器,并依次更替控制输入数据的等相位差时钟,可以得到FFE所需的多路延迟数据。为了均衡由于信道的各种非理想因素产生的信号频率上的衰减,采用IDAC控制抽头系数的三抽头前馈均衡器对线路衰减进行均衡,提出使用MATLAB对信道衰减进行建模,并以此来设计滤波器的方法,快速简便确定抽头系数,将抽头系数映射到IDAC的不同控制位从而获得针对不同信道衰减的FFE。最终,设计基于TSMC 28nm CMOS工艺实现。仿真结果显示数据传输达10 Gbps时高速串行器逻辑正常,数据眼图良好,输出抖动在0.09 UI,满足高速背板通信电路的标准。In view of the signal integrity problem of 10 Gbps high-speed SerDes sender, the design of key modules is optimized, including high-speed serializers, feed-forward equalizer circuits(FFE),current digital converter(IDAC)control circuits, etc. In order to reduce the requirement of clock performance, the traditional current mode logic(CML)serializer is improved. By adjusting the clock duty cycle, a quarter-rate serializer is designed, and the control input is replaced in turn. The equal phase difference clock of the data can obtain the multiple delay data required by the FFE. In order to balance the attenuation on the signal frequency caused by various non-ideal channel factors, the three-tap feed-forward equalizer of the IDAC control tap coefficient is used to equalize the line attenuation, and the method of channel attenuation is proposed to model the channel attenuation by using MATLAB,and the method of filter is designed to determine the tap coefficient quickly and easily, then the tap coefficient is mapped to different control bits of the IDAC to obtain FFE for different channel attenuation. The design is implemented with TSMC 28 nm CMOS process, the simulation results show that the high-speed serializer logic is normal when the data transmission reaches 10 Gbps, the data eye diagram is good, the output jitter is at 0.09 UI,and the standard of high-speed backplane communication circuit is met.

关 键 词：多通道高速串行器 高速SerDes 前馈均衡器 电流数模转换器 

分 类 号：TN76[电子电信—电路与系统] TN83