基于视频阵列处理器的3D-HEVC视差估计算法并行设计与实现  

PARALLEL DESIGN AND IMPLEMENTATION OF 3D-HEVC DISPARITY ESTIMATION ALGORITHM BASED ON VIDEO ARRAY PROCESSOR

作　　者：蒋林 冯茹 Jiang Lin;Feng Ru(School of Computer Science and Technology,Xi’an University of Science and Technology,Xi’an 710121,Shaanxi,China)

机构地区：[1]西安科技大学计算机科学与技术学院,陕西西安710121

出　　处：《计算机应用与软件》2023年第7期260-265,281,共7页Computer Applications and Software

基　　金：国家自然科学基金重点项目(61834005/F0402);陕西省自然科学基金项目(2020JM-525)。

摘　　要：三维高效视频编码(3D High Efficiency Video Coding,3D-HEVC)中视差估计算法存在处理数据量大、运算时间长和资源消耗大的问题,进一步提高算法执行效率对于3D-HEVC的推广应用具有十分重要的意义。在深入分析视差估计算法的并行性的基础上,基于项目组开发的视频阵列处理器(DPR-CODEC),提出一种新的并行实现方案。在可重构阵列结构中完成了视差估计算法的并行映射、功能仿真和FPGA测试,显著减少了视差估计算法的执行时间。实验结果表明,所提出的并行实现方案相比于串行单PE执行时间节省了59%,基于可编程可重构阵列的并行实现在具有较高的执行效率的同时也具有较好的灵活性。The disparity estimation algorithm in 3D high efficiency video coding(3D-HEVC)has the problems of large amount of processing data,long computing time and high resource consumption.Further improving the efficiency of algorithm execution is very important for the promotion and application of 3D-HEVC.Based on the in-depth analysis of the parallelism of the disparity estimation algorithm,this paper proposes a new parallel implementation scheme based on the video array processor(DPR-CODEC)developed by the project team.In the reconfigurable array structure,the parallel mapping,functional simulation and FPGA test of the disparity estimation algorithm were completed,which significantly reduced the execution time of the disparity estimation algorithm.The experimental results show that the proposed parallel implementation scheme saves 59%of the execution time compared with the serial single PE.The parallel implementation based on programmable reconfigurable array has higher execution efficiency and better flexibility.

关 键 词：三维高效率视频编码 并行性 视差矢量 阵列处理器 

分 类 号：TP302.7[自动化与计算机技术—计算机系统结构]