基于RISC-V的SM2点乘运算协处理器设计  

Design of SM2 Point Multiplication Coprocessor Based on RISC V

作　　者：孙子婷 韩跃平[1] 唐道光 Sun Ziting;Han Yueping;Tang Daoguang(School of Instrument and Electronics,North University of China,Taiyuan 030051,China;100 Trust Information Technology Co.,Ltd.)

机构地区：[1]中北大学信息与通信工程学院,太原030051 [2]百信信息技术有限公司

出　　处：《单片机与嵌入式系统应用》2023年第8期28-31,共4页Microcontrollers & Embedded Systems

摘　　要：针对SM2国密算法在有限域上大数运算结构复杂、运算开销大的问题,通过研究SM2国密算法在二元扩域下的椭圆曲线点乘运算及其相关基础运算,设计了一种基于RISC-V指令集的椭圆曲线点乘运算加速协处理器。协处理器采用三级流水线结构,提高了计算效率。处理器内部集成9条自定义指令,可协助支持RISC-V的主处理器快速完成SM2国密算法。Vivado仿真结果表明,本设计各流水级功能正常,将协处理器烧录至Xilinx XC7A100T FPGA上,在200 MHz频率下运行结果正确,达到预期目标。In response to the complex structure and high computational overhead of the SM2 national secret algorithm in finite fields,the elliptic curve point multiplication and related basic operations of the SM2 national secret algorithm in binary extended domains are studied,and designs an elliptic curve point operation acceleration coprocessor based on the RISC-V instruction set.The coprocessor adopts a three-level pipeline structure,which improves computational efficiency.The processor integrates 9 custom instructions internally,which can assist the main processor supporting RISC-V to quickly complete the SM2 national security algorithm.The simulation results of Vivado show that the functions of each pipeline stage in this design are normal.The coprocessor is burned onto the Xilinx XC7A100T FPGA and runs correctly at a frequency of 200 MHz,achieving the expected goals.

关 键 词：RISC-V 协处理器 多倍点运算 二元扩域 

分 类 号：TN492[电子电信—微电子学与固体电子学]