用于微光CMOS图像传感器的相关多采样技术  

Correlated Multiple Sampling Technique for Low-Light CMOS Image Sensors

作　　者：李少蒙 聂凯明 徐江涛 Li Shaomeng;Nie Kaiming;Xu Jiangtao(School of Microelectronics,Tianjin University,Tianjin 300072,China)

机构地区：[1]天津大学微电子学院,天津300072

出　　处：《激光与光电子学进展》2023年第12期401-407,共7页Laser & Optoelectronics Progress

基　　金：国家重点研发计划(2019YFB2204200)。

摘　　要：为了提高用于低噪声CMOS图像传感器的单斜模数转换器(SS ADC)的量化速度,提出一种基于SS ADC的根据输入光强确定采样次数的相关多次采样(CMS)技术。利用数字模拟转换器(DAC)输出信号的差分特性,根据输入电压大小,分别按照不同的方式选择正/负斜坡输入到比较器中。当输入电压信号较小时,控制斜坡形状,使采样次数为4;当输入电压信号较大时,使采样次数为2。采用110 nm的CMOS工艺,时钟频率为400 MHz,行转换时间为23μs,分辨率为11位,量化范围为1 V内。仿真结果表明:所提技术的微分非线性(DNL)达+0.6/-0.3LSB,LSB指最低有效位,积分非线性(INL)达+0.7/-0.9LSB;最低噪声为82μV;与传统的采样次数为4的CMS技术相比,在不增加低照度下噪声的同时,将A/D转换周期节约了13μs。To enhance the conversion speed of single-slope analog-to-digital converter(SS ADC)for low-noise CMOS image sensors,this study proposes a correlated multiple sampling(CMS)method based on SS ADC,which entails estimating the sampling time based on the input light intensity.Using the differential characteristic of the output signal of a digital-to-analog converter(DAC),the positive/negative ramp was selected according to input voltage.When the input voltage is low,the ramp shape was regulated such that there were four sampling times;when the input voltage is high,the sampling time was set to two.This design is based on 110-nm node CMOS process,and the clock frequency is 400 MHz,line conversion time is 23μs,resolution is 11 bit,and quantization range is 1 V.The simulation results reveal that the differential nonlinearity(DNL)of this design is+0.6/−0.3LSB(LSB is least significant bit),and the integral nonlinearity(INL)is+0.7/−0.9LSB,with 82μV being the minimum noise.Compared with conventional CMS method with sampling number of four,the A/D conversion time of the proposed method is saved by 13μs without increasing noise under low light.

关 键 词：CMOS图像传感器 单斜模数转换器 低噪声 相关多次采样 微光探测 

分 类 号：TP212[自动化与计算机技术—检测技术与自动化装置]