一种基于资源优化的DDC设计及实现  

Design and Implementation of a DDC Based on Resource Optimization

作　　者：魏静[1] WEI Jing(East China Research Institute of Electronic Engineering,Hefei 230088,China)

机构地区：[1]中国电子科技集团公司第三十八所,安徽合肥230088

出　　处：《电声技术》2023年第3期119-121,共3页Audio Engineering

摘　　要：数字接收系统中,对输入的射频信号直接中频采样后进行数字下变频(Digital Down Converter,DDC),有效减少了硬件模拟设备的数量,提高了系统的可靠性和稳定性。针对高速数字下变频存在的采样率高、资源消耗高等难点,利用滤波器系数的对称性特点设计了一种在不降低处理速度的前提下,减少现场可编程门阵列(Field ProgrammableGate Array,FPGA)内部处理单元个数,实现功耗降低的有限冲击响应(Finite Impulse Response,FIR)滤波器,并在FPGA中得到了实现。实验结果表明,该方法性能优异,可大幅节省资源,具有较高的工程实用价值。In the digital receiving system,the input RF signal is directly sampled if and then subjected to Digital Down Converter(DDC),which effectively reduces the number of hardware analog devices and improves the reliability and stability of the system.Aiming at the difficulties of high sampling rate and high resource consumption in high-speed digital down-conversion,a Finite Impulse Response(FIR)filter is designed and implemented in FPGA without reducing the processing speed.The experimental results show that this method has excellent performance,can greatly save resources,and has high engineering practical value.

关 键 词：数字下变频(DDC) 有限冲击响应(FIR)滤波器 现场可编程门阵列(FPGA) 

分 类 号：TN773[电子电信—电路与系统]