一种FPGA的高速IP验证方法研究与实现  

Research and Implementation of a High Speed IP Authentication Method for FPGA

作　　者：陈龙 缪泽宇 解维坤 葛云侠 宋国栋 CHEN Long;MIAO Zeyu;XIE Weikun;GE Yunxia;SONG Guodong(The 58th Research Institute of China Electronics Technology Group Corporation,Wuxi 214035,China;School of Automation Engineering,University of Electronic Science and Technology of China,Chengdu 611731,China;School of Electronic&Information Engineering,Nanjing University of Information Science&Technology,Nanjing 210044,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214072 [2]电子科技大学自动化学院,四川成都611731 [3]南京信息工程大学电子与信息工程学院,江苏南京210044

出　　处：《电子质量》2023年第7期78-83,共6页Electronics Quality

摘　　要：当前高速串行通信技术已被广泛地应用于电子、计算机等各个领域,高速信号质量的好坏决定了整个系统的好坏,因此对高速信号的验证变得极其重要。现场可编程门阵列(FPGA)作为高速串行通信中不可取代的高性能新品,对电子信息系统的先进性、安全性和可靠性起到决定性作用。FPGA内部集成多个高速知识产权(IP),因此对FPGA的高速IP进行验证测试变得尤为重要。通过误码率测试仪(IBERT)核来监控和评估高速IP,介绍了IBERT的基本功能、实现方法,以及高速串行收发器(GTX)的工作原理和验证方法。同时基于KC705平台搭建验证环境,使用IBERT核调整激励参数,对FPGA的高速串行接口进行验证,并对其误码、抖动和眼图进行详细的分析。实验证明,该方法大大地提高了IP的评估质量和效率。At present,high-speed serial technology is widely used in electronic,computer and other fields,and the quality of high-speed signal determines the quality of the whole system,so the verification of high-speed signals becomes extremely important.Field programmable gate array(FPGA),as an irreplaceable high-performance product in high-speed serial communication,plays a decisive role in the advancement,security and reliability of electronic information systems.FPGA is internally integrated with multiple high-speed intellectual property(IP),so it is particularly important to verify and test the high-speed IP of FPGA.High-speed IP is monitored and evaluated through the integrated bit error ratio tester(IBERT)core,the basic functions and implementation methods of IBERT,as well as the working principle and verification methods of Gigabit Transceiver(GTX)are introduced.At the same time,the verification environment is built based on KC705 platform,and IBERT core is used to adjust excitation parameters to verify the high-speed serial interface of FPGA,and its bit error,jitter and eye diagram are analyzed in detail.The experiment proves that the method greatly improves the quality and efficiency of IP evaluation.

关 键 词：现场可编程门阵列 误码率测试仪核 GTX 高速串行收发器 高速串行信号测试 

分 类 号：TN492[电子电信—微电子学与固体电子学]