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作 者:赵思捷 高尚尚 王如刚[1] 王媛媛[1] 周锋[1] 郭乃宏 ZHAO Sijie;GAO Shangshang;WANG Rugang;WANG Yuanyuan;ZHOU Feng;GUO Naihong(School of Information Technology,Yancheng Institute of Technology,Yancheng Jiangsu224051,China;Yancheng Xiongying Precision Machinery Company Limited,Yancheng Jiangsu 224006,China)
机构地区:[1]盐城工学院信息工程学院,江苏盐城224051 [2]盐城雄鹰精密机械有限公司,江苏盐城224006
出 处:《盐城工学院学报(自然科学版)》2023年第2期55-60,共6页Journal of Yancheng Institute of Technology:Natural Science Edition
基 金:国家自然科学基金项目资助(61673108);江苏省研究生实践创新计划项目资助(SJCX21_1517);江苏省高等学校自然科学研究重大项目资助(19KJA110002)。
摘 要:针对CPU进行图像处理已经无法满足系统实时性需求这一情况,提出了一种基于HLS和PYNQ的图像处理硬件加速器设计。该设计利用了FPGA具有数据并行处理的优势,克服了FPGA不易开发、移植性较差的缺陷。首先选择图像缩放处理算法作为实验的测试对象;然后在ZYNQ平台上根据软硬件协同的特点分配不同的系统任务,通过HLS开发工具使用C++实现和优化图像处理算法,并转化成RTL文件,再打包成IP核输出;在Vivado2018.3上搭建硬件实验平台,通过JupyterLab对实验进行验证和分析。结果表明,缩放算法的处理速度由CPU端的1110ms缩减为FPGA端的213ms,执行速度提升了5倍。In view of the fact that image processing by CPU can no longer meet the real-time requirements of the system,a hardware accelerator design for image processing based on HLS and PYNQ is proposed.This design makes use of the advantages of data parallel processing of FPCA,and overcomes the defects of difficult development and poor portability of FPGA.First,the Image scaling processing algorithm is selected as the test object of the experiment.Then,different system tasks are assigned on ZYNQ platform according to the characteristics of software and hardware cooperation.The image processing algorithm is realized and optimized by using C++ through HLS development tools,which is converted into RTL files and then packaged into IP cores for output.A hardware experimental platform was built on Vivado2018.3,and the experiment was verified and analyzed by Jupyter Lab.The results show that the processing speed of the scaling algorithm has been reduced from 1110 ms on the CPU side to 213 ms on the FPGA side,and the execution speed is increased by 5 times.
关 键 词:FPGA 缩放算法 HLS PYNQ Jupyter Lab
分 类 号:TP183[自动化与计算机技术—控制理论与控制工程]
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