应用级兼容RISC-V的混合指令集处理器  

A hybrid ISA processor compatible with RISC-V at application level

作　　者：孙彩霞[1] 隋兵才[1] 邓全[1] 郑重[1] 倪晓强[1] 王永文[1] SUN Cai-xia;SUI Bing-cai;DENG Quan;ZHENG Zhong;NI Xiao-qiang;WANG Yong-wen(College of Computer Science and Technology,National University of Defense Technology,Changsha 410073,China)

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2023年第8期1347-1353,共7页Computer Engineering & Science

基　　金：高层次科技创新人才工程入选自主科研项目(22-TDRCJH-02-006);国家国防科技工业局国防科技重点实验室稳定支持项目(WDZC20215250111);“十四五”全军共用信息系统装备预先研究项目(31513010103)。

摘　　要：指令集架构的改变会导致处理器硬件平台发生变化,面向旧硬件平台编译的二进制应用程序将无法在新的硬件平台上继续运行。提出了一种应用级兼容多种指令集的混合指令集架构,基于该混合指令集架构的处理器可原生运行多种指令集的应用,能有效避免程序开发移植的重复工作或二进制翻译执行的性能损失。在自主研发的一款处理器基础上实现了应用级兼容RISC-V的混合指令集处理器。与单一指令集相比,应用级支持2种指令集带来的硬件开销仅增加了0.45%。FPGA原型系统成功启动了面向混合指令集架构移植的操作系统,并能正确运行2种指令集的应用,验证了混合指令集架构思想的可行性。RISC-V指令集下,Coremark性能为5.58/MHz,SPECint2006的性能为8.44/GHz,SPECfp2006的性能为10.75/GHz。Changes in the instruction set architecture will result in changes in the processor hardware platform,and binary applications compiled for the old hardware platform will not be able to continue running on the new hardware platform.In this paper,a hybrid instruction set architecture compatible with multiple instruction sets at application level is proposed,and the processor based on the hybrid instruction set architecture can natively run multiple instruction set applications,which can effectively avoid the repetitive work of program developing and porting or the performance loss of the binary translation execution.Based on a self-developed processor,a hybrid instruction set processor compatible with RISC-V at application level is implemented.Compared with a single instruction set,the hardware overhead of supporting for two instruction sets at application level is only increased by 0.45%.The FPGA prototype system successfully boots the operating system ported to the hybrid instruction set architecture,and can correctly run the application based on each instruction set,which verifies the feasibility of the hybrid instruction set architecture idea.Under RISC-V instruction set,the processor achieves 5.58/MHz for Coremark,8.44/GHz for SPECint2006 and 10.75/GHz for SPECfp2006.

关 键 词：混合指令集 RISC-V 处理器 应用级 兼容 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]