基于TSV的3D IC层次化物理实现技术  

A Hierarchy Physical Design Technique for TSV-based 3D Integrated Circuits

作　　者：迟元晓 王志君[3] 梁利平[3] 刘丰满[1] 邱昕[1] CHI Yuanxiao;WANG Zhijun;LIANG Liping;LIU Fengman;QIU Xin(Institute of Microelectronics of Chinese Academy of Science,Beijing 100029,China;School of Integrated Circuits,University of Chinese Academy of Science,Beijing 100190,China;School of Integrated Circuits,Beijing University of Posts and Telecommunications,Beijing 100876,China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学集成电路学院,北京101408 [3]北京邮电大学集成电路学院,北京100876

出　　处：《湖南大学学报（自然科学版）》2023年第8期134-140,共7页Journal of Hunan University:Natural Sciences

基　　金：国家自然科学基金资助项目(U21A20504)。

摘　　要：随着集成电路特征尺寸逼近物理极限,硅通孔(TSV)实现层间互连的三维集成电路(3D IC)成为延续摩尔定律的一种趋势.但现有集成电路设计工具、工艺库、设计方法尚不成熟,难以实现三维集成中超大尺寸基板芯片的时序收敛问题.为此,本文提出了一种利用现有传统的EDA工具完成基于TSV的3D IC物理设计的流程.首先,用热应力模型将三维硅通孔投影成二维阻挡层,从而将三维集成电路设计转化成若干含阻挡层的二维集成电路分别实现;其次,针对超大尺寸基板芯片的时序收敛困难问题,提出了一种标准单元布局方法,通过在版图中划定若干固定放置区用于限定关键时序单元的摆放,并迭代确定这些关键单元在固定放置区中的位置,实现大尺寸芯片的时序收敛.基于所提出的三维集成电路设计流程完成了一款三维集成的网络路由芯片基板芯片的设计,结果表明,相比传统的设计流程,提出的3D IC物理设计流程可使超大尺寸基板芯片从时序无法收敛优化到可收敛并满足时序要求,验证了所提出的3D IC物理设计流程的可行性.As the feature size of integrated circuits approaches the physical limit,through-silicon-via-based three-dimensional integrated circuits(3D ICs)have become a trend to continue Moore’s Law.However,existing EDA tools,technology libraries and design methodologies are far from mature enough to achieve timing convergence of ultra-large-size interposers of 3D ICs.To address this issue,a new implementation flow for physical design of TSV-based 3D ICs using conventional EDA tools is proposed.Firstly,a thermal stress model is employed to project the silicon vias into 2D blockages,thereby dividing the entire 3D IC into several 2D ICs with blockages.Each of these 2D ICs can be implemented by traditional EDA tools,respectively.Secondly,to address the timing convergence difficulties of ultra-large-size interposers,this paper puts forward a new method,which first creates a couple of bounds throughout the layout and then iteratively moves pipeline cells affecting timing greatly between the bounds.Cells in bounds are not permitted to move during placement.This approach ensures a more organized initialization and reduces disorder,thus enabling convergence to be achieved.The whole flow is applied to the physical implementation of a practical 3D integrated circuit.The experimental results show that the proposed flow can optimize both the worst negative slack and the total negative slack by more than 98%compared with the original flow.Consequently,timing convergence is accomplished,and the feasibility of the proposed design flow is proved.

关 键 词：硅通孔 三维集成电路 大尺寸芯片 版图设计 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]