基于共享存储技术的乱序TCP分段重排电路设计  

Design of Out-of-Order TCP Segment Rearrangement Based on Shared Memory Technology

作　　者：鲁铭洋 乔庐峰 张栋 LU Mingyang;QIAO Lufeng;ZHANG Dong(Army Engineering University of PLA,Nanjing 210001,China)

机构地区：[1]陆军工程大学,江苏南京210001

出　　处：《通信电源技术》2023年第11期58-61,共4页Telecom Power Technology

摘　　要：传输控制协议(Transmission Control Protocol,TCP)处理引擎可以广泛应用于数据中心的各类型服务器,降低处理器负荷。为提高TCP协议处理引擎处理数据的分段效率,设计了一种基于共享存储技术的乱序TCP分段重排电路,其采用静态随机存储器(Static Random Access Memory,SRAM)存储,具有结构简单、存储资源利用率高、低时延的特性,可有效克服内容寻址存储器(Content Addressable Memory,CAM)或三态内容可寻址存储器(Ternary Content Addressable Memory,TCAM)高功耗以及可扩展性差的缺点,同时满足上千条连接的工作需求;分析了电路的具体结构、关键调度算法和工作流程,并进行了仿真。电路基于Xilinx ZYNQ 7000系列的现场可编程门阵列(Field-Programmable Gate Array,FPGA)实现,对主要硬件资源消耗进行了综合分析。The Transmission Control Protocol(TCP)processing engine can be widely applied to various types of servers in data centers,reducing the processor load.To improve the efficiency of data segment in the TCP protocol processing engine,an out-of-order TCP segment rearrangement circuit based on shared storage technology is designed.It adopts Static Random Access Memory(SRAM)storage,has the characteristics of simple structure,high storage resource utilization rate and low delay,and can effectively overcome the shortcomings of high power consumption and poor scalability of Content Addressable Memory(CAM)or Ternary Content Addressable Memory(TCAM)devices.It can meet the working requirements of thousands of connections at the same time.The structure,key scheduling algorithm and workflow of the circuit are analyzed and simulated.The circuit is implemented based on Xilinx ZYNQ 7000 series Field-Programmable Gate Array(FPGA),and the main hardware resource consumption is analyzed comprehensively.

关 键 词：共享存储 哈希查找 乱序重排 传输控制协议(TCP)分段 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]