DDR4高速并行总线的信号完整性仿真研究  

Research on signal integrity simulation of DDR4 high-speed parallel bus

作　　者：伍颖 WU Ying(The 34th Research Institute of China Electronics Tech,Guilin,Guangxi 541000,China)

机构地区：[1]中国电子科技集团公司第三十四研究所,广西桂林541000

出　　处：《计算机应用文摘》2023年第16期71-73,共3页Chinese Journal of Computer Application

摘　　要：文章主要采用仿真测试的方式,对反射与串扰两种影响DDR4高速并行总线信号完整性的因素进行重点分析,并找出提升信号完整性的PCB布线方法,旨在为高速并行总线信号完整性问题的解决带来启发。This paper mainly adopts the method of simulation test,focuses on the analysis of the two factors that affect the signal integrity of DDR4 high-speed parallel bus,and finds out the PCB wiring method to improve the signal integrity,hoping to solve the problem of high-speed parallel bus signal integrity.

关 键 词：DDR4 高速并行总线 信号完整性 信道仿真 

分 类 号：TN41[电子电信—微电子学与固体电子学]