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作 者:李建[1] 马红波[1] 唐林[1] LI Jian;MA Hongbo;TANG Lin(School of Electrical Engineering,Southwest Jiaotong University,Chengdu 611756,China)
机构地区:[1]西南交通大学电气工程学院,四川成都611756
出 处:《电工技术》2023年第13期66-73,共8页Electric Engineering
基 金:国家自然科学基金(编号51777176,61733015)。
摘 要:数据中心48 V母线为VRM的设计带来高降压比(48 V/1.0 V)、超低压大电流和超快动态响应的三大技术挑战。为进一步提高48 V VRM的转换效率和功率密度,在论述各种解决方案的基础上,以两级式结构为参考,研究前级开关谐振腔变换器的MHz设计、优化与实现。在分析工作原理的基础上,考虑谐振回路寄生电阻和飞跨电容为有限值对谐振频率的影响,因参数容差致使开关管未实现ZCS时需在死区时间将谐振电流恢复至零,得到谐振参数约束;最后根据1 MHz开关谐振腔变换器的损耗特点,选择合适器件。实验室搭建了一台48 V输入、12 V/25 A输出、1 MHz原理样机,功率密度达57.79 W/cm 3(947 W/in 3),测试峰值和满载效率分别高达98.19%和94.8%,验证了设计方案的可行性和先进性。The 48 V bus in data center brings three technical challenges for VRM design:high step-down ratio(48 V/1.0 V),ultra-low voltage and high current,and ultra-fast dynamic response.In order to further improve the conversion efficiency and power density of 48 V VRM,based on the discussion of various solutions,the MHz design,optimization and implementation of the pre-switching resonator converter are studied with the two-stage structure as a reference.Based on the analysis of the working principle,the influence of the resonant loop parasitic resistance and the flying capacitance as finite values on the resonant frequency was considered.When the switch transistor does not achieve ZCS due to parameter tolerance,it is necessary to restore the resonant current to zero in the dead time to obtain the resonance parameter constraint.Finally,according to the loss characteristics of the 1 MHz switching cavity converter,the appropriate device is selected.A 48 V input,12 V/25 A output,1 MHz prototype with a power density of 57.79 W/cm 3(947 W/in 3)was built in the laboratory.The test peak and full load efficiency were as high as 98.19%and 94.8%,respectively,which verified the feasibility and advanced nature of the design scheme.
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