基于FCM flow的小规模数字电路芯片测试  

Small-scale digital circuit chip testing based on FCM flow

作　　者：崔震 周立阳 刘萌 赵禹 王学德 Cui Zhen;Zhou Liyang;Liu Meng;Zhao Yu;Wang Xuede(PEAK,Shanghai 201210,China)

机构地区：[1]思瑞浦微电子科技(上海)有限责任公司,上海201210

出　　处：《电子技术应用》2023年第8期24-29,共6页Application of Electronic Technique

摘　　要：随着芯片工艺的不断演进,数字芯片的规模急剧增加,测试成本进一步增加。目前先进的DFT技术已应用于大规模SoC芯片的测试,包括扫描路径设计、JTAG、ATPG(自动测试向量生成)等。但对于一些小规模集成电路,插入扫描链等测试电路会增加芯片面积并增加额外的功耗。对于这种芯片,功能case生成的pattern可用于检测制造缺陷和故障。因此,需要一些方法来验证覆盖率是否达到了目标。Verisium manager工具依靠Xcelium的故障仿真引擎和Jasper功能安全验证应用程序(FSV)可以解决这个问题。它为ATE(自动测试设备)pattern的覆盖率分析提供了一个新的思路。With the advance of the chip process,the scale of digital chips has increased sharply,and the cost of testing has further increased.Advanced DFT technology has been used on large scale SoC chips,including scan path design,JTAG,ATPG(Automatic Test Pattern Generation)and more.However,for some small scale integrated circuits(analog front end chips for example),inserting test circuits,such as scan chains,will increase chip area and add additional power consumption.For this kind of chip,the test pattern generated from functional simulation cases can be used to detect the manufacturing defects and failures.Therefore,there should be some methodology to verify if the coverage has met the goal,especially for automotive chips.Cadence Verisium Manage Safety Client,relying on core engines of Xcelium Fault Simulator and the Jasper Functional Safety Verification App(FSV)can solve this problem.It provides a credible coverage for ATE(Automated Test Equipment)pattern.

关 键 词：DFT 覆盖率 Verisium manager Xcelium fault simulator JASPER 

分 类 号：TN402[电子电信—微电子学与固体电子学]