一种基于Quantus-reduce加速模拟仿真验证分析的解决方案  

A solution to accelerate simulation verification and analysis based on Quantus-reduce

作　　者：李嘉欣 黄亚平 胡劼 凌秋婵 杨晓晨 Li Jiaxin;Huang Yaping;Hu Jie;Ling Qiuchan;Yang Xiaochen(Sanechips Technology Co.,Ltd.,Shenzhen 518055,China;National Key Laboratory of Radio Frequency Heterogeneous Integration,Shenzhen 518060,China;State Key Laboratory of Mobile Network and Mobile Multimedia Technology,Shenzhen 518055,China;Cadence Design Systems,Inc.,Shanghai 200120,China)

机构地区：[1]深圳市中兴微电子技术有限公司,广东深圳518055 [2]射频异质异构集成全国重点实验室,广东深圳518060 [3]移动网络和移动多媒体技术国家重点实验室,广东深圳518055 [4]上海楷登电子科技有限公司,上海200120

出　　处：《电子技术应用》2023年第8期42-46,共5页Application of Electronic Technique

摘　　要：随着半导体技术的进步,芯片的设计规模不断扩大,这使得电路设计需要考虑的寄生效应更加复杂,电路的后仿真工作也变得更加繁重。介绍了如何应用Cadence公司的寄生抽取工具Quantus进行post-layout寄生抽取,利用Quantus的Standalone Reduction(简称Qreduce)功能对后仿网表进行精简,以达到缩减网表的规模,提高仿真速度的目的。Cadence的Qreduce功能是通过数学的运算,将RC网络进行等效运算,以减少节点,从而达到缩减网表的规模,但同时保证了不会对精度造成比较大的损失。从后仿网表的缩减程度、仿真精度的影响、仿真速度以及内存消耗等方面进行论述,给出关键对比指标。With the continuous development of semiconductor technology,the scale of chip design is increasing.That makes much more complicated parasitic need to be considered in designs and also makes post-simulation cost much more loading.This article will discuss how to use Cadence's parasitic extraction tool Quantus for post-layout parasitic extraction,and use Quantus'Standalone Reduction(Qreduce)function to simplify the post-imitation netlist to reduce the size of the netlist and increase the speed of simulation.Cadence's Qreduce function is to perform equivalent operations on the RC network through mathematical operations to reduce the number of nodes,thereby reducing the size of the netlist,but at the same time ensuring that the accuracy will not cause a relatively large loss.This article will discuss the degree of post-simulation netlist reduction,the impact of simulation accuracy,simulation speed and memory consumption,and give key comparison indicators.

关 键 词：Qreduce 后仿网表精简 仿真精度 仿真速度 

分 类 号：TN402[电子电信—微电子学与固体电子学]