DDR5仿真精度研究及在内存升级中的应用  

Research on DDR5 simulation accuracy and application in memory upgrading

作　　者：黄刚 姜杰 吴均 Huang Gang;Jiang Jie;Wu Jun(Shenzhen Edadoc Technology Co.,Ltd.,Shenzhen 518051,China)

机构地区：[1]深圳市一博科技股份有限公司,广东深圳518051

出　　处：《电子技术应用》2023年第8期53-58,共6页Application of Electronic Technique

摘　　要：使用Cadence公司的SystemSI对DDR信号通道进行整体仿真,同时,借助一博科技自研的Interposer夹具进行测试,经过多次的仿真测试拟合,所介绍的DDR仿真测试方法可以达到较高的精度。随着对内存带宽的需求不断提升,作为当前主流的DDR4局限性日益明显,通过具体案例说明了DDR5信号完整性提升的具体技术,并通过仿真对比,展示了DDR5在内存升级过程中的优势。This paper uses Cadence's SystemSI for DDR whole channel simulation,and the interposer fixture developed by EDADOC Technology for testing.After multiple verification simulation with testing data,the DDR simulation and testing method offered by this paper can achieve high accuracy.With the increasing demand for memory bandwidth,the limitations of DDR4,the current mainstream,are becoming increasingly obvious.This paper illustrates the specific technologies for improving the signal integrity of DDR5 through specific cases,and demonstrates the advantages of DDR5 in the process of memory upgrading through simulation comparison.

关 键 词：DDR4 DDR5 SystemSI Interposer DFE ODT 

分 类 号：TN402[电子电信—微电子学与固体电子学]