双端口SRAM抗写干扰结构的优化设计  

Optimization Design of Dual-Port SRAM Anti-Write Interference Structure

作　　者：李学瑞 秋小强 刘兴辉[1] Li Xuerui;Qiu Xiaoqiang;Liu Xinghui(School of Physics,Liaoning University,Shenyang 110036,China;Shandong CWISE Microelectronics Technology Co.,Ltd.,Jinan 250100,China)

机构地区：[1]辽宁大学物理学院,沈阳110036 [2]山东芯慧微电子科技有限公司,济南250100

出　　处：《半导体技术》2023年第7期617-623,共7页Semiconductor Technology

基　　金：辽宁省自然科学基金资助项目(2021-MS-148)。

摘　　要：针对双端口静态随机存储器(SRAM)通常存在写干扰而导致数据写入困难的问题,基于经典位线电平复制技术提出了一种新型的位线电平复制结构。基于SMIC 28 nm CMOS工艺对位线电平复制结构进行设计,通过优化控制逻辑的组合电路,缩短位线电平复制操作的开启时间,提高了数据写入SRAM的速度,使设计的SRAM可在更高频率下正常工作,同时降低了动态功耗。仿真结果显示,在0.9 V工作电压下,相对于经典位线电平复制结构,采用新结构设计的SRAM的写入时间缩短了约27.4%,动态功耗降低了约48.1%,抗干扰能力得到显著提升。Aiming at the problem that dual-port static random access memory(SRAM)usually has difficulty in data writing due to write interference,a new bit line level replication structure was proposed based on the classical bit line level replication technology.Based on SMIC 28 nm CMOS process,the bit line level replication structure was designed.By optimizing the combination circuit of control logic,the turn-on time of bit level replication operation was shortened,the speed of data writing to SRAM was improved,so that the designed SRAM can operate normally at a higher frequency,while reducing dynamic power consumption.The simulation results show that at a working voltage of 0.9 V,compared with the classical bit line level replication structure,the write time of the SRAM designed with the new structure is shortened by about 27.4%,the dynamic power consumption is reduced by about 48.1%,and the anti-interference ability is significantly improved.

关 键 词：双端口静态随机存储器(SRAM) 位线电平复制 写干扰 控制逻辑 数据写入时间 

分 类 号：TN791[电子电信—电路与系统] TN432