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作 者:陶玉辉 杜高明 郭文杰 李桢旻 王晓蕾 TAO Yuhui;DU Gaoming;GUO Wenjie;LI Zhenmin;WANG Xiaolei(School of Microelectronics,Hefei University of Technology,Hefei 230009,CHN)
出 处:《半导体光电》2023年第3期436-443,共8页Semiconductor Optoelectronics
基 金:国家重点研发计划项目(2018YFB2202604);安徽省高校协同创新项目(GXXT-2019-030)。
摘 要:针对现有极化码软输出译码器存在的高资源消耗与低资源效率,设计了一种快速低复杂度软取消(Fast Reduced Complexity Soft-Cancelation,Fast-RCSC)译码算法及其译码器硬件架构。Fast-RCSC算法对内部特殊结点进行完整计算,在减少译码周期的同时仍有较好译码性能。基于不同特殊结点公式之间存在相似性,进而通过对引入的特殊结点模块进行计算结果复用以及计算模块分时复用,减少特殊结点模块资源消耗。通过共用存储单元以及对不足存储单元数据宽度的数据进行合并,降低存储资源消耗。在华润上华(Central Semiconductor Manufacturing Corporation,CSMC)180 nm工艺下综合结果表明,设计的译码器在码长为1 024的情况下,面积为2.92 mm^(2),资源效率为245.2 Mbps/mm^(2),相比现有软输出译码器有不同程度的提升。The existing polar code soft-output decoders suffer from high resource consumption and low resource efficiency of the hardware implementation.In this paper,a Fast-RCSC decoding algorithm and its decoder hardware architecture were designed.The Fast-RCSC algorithm performed complete calculations on internal special nodes,reducing the decoding cycle while maintaining high decoding performance.Based on the similarity between different special node formulas,the resource consumption of special node modules was reduced by reusing calculation results of the introduced special node modules and reusing time-division multiplexing scheme of calculation modules.The storage resource consumption was reduced by sharing storage units and merging data with bit width lower than the limit.The synthesis results in CSMC 180 nm process show that the designed decoder has an area size of 2.92 mm^(2) and a resource efficiency of 245.2 Mbps/mm^(2) when the code length is 1 024 bits,which demonstrates different degrees of improvement compared to existing polar code soft-output decoders.
关 键 词:极化码译码器 软输出 资源效率 资源复用 专用集成电路
分 类 号:TN47[电子电信—微电子学与固体电子学]
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