基于树形Mux的逻辑电路优化  

Mux tree-based logic circuit optimization

作　　者：于宗源 廖春柳 胡张 王伦耀[1] YU Zongyuan;LIAO Chunliu;HU Zhang;WANG Lunyao(Faculty of Electrical Engineering and Computer Science,Ningbo University,Ningbo 315211,China)

机构地区：[1]宁波大学信息科学与工程学院,浙江宁波315211

出　　处：《宁波大学学报（理工版）》2023年第5期69-75,共7页Journal of Ningbo University：Natural Science and Engineering Edition

基　　金：国家自然科学基金(61871242);浙江省自然科学基金(LY19F040004)。

摘　　要：为实现用case语句描述的逻辑电路的面积和延迟优化,提出了一种基于树形Mux的逻辑电路优化方法.该方法先将case语句转换为树形Mux,通过合并case语句实现Mux树中Mux门的个数和层级减少,并通过化简地址逻辑实现地址再编码电路的精简,进而实现映射后电路面积与延迟的优化.提出的算法使用C++语言实现,电路面积和延迟优化结果由常用学术开源EDA工具abc,结合国内EDA公司提供的映射库得到.实验结果表明,相比于abc工具,使用该方法得到的面积和延迟优化分别提升了26%和21%.In order to optimize the area and delay of logic circuits described using case statements,an optimization method based on Mux tree is proposed.The method first converts case statements into a Mux tree,followed by reducing the number of Muxes and levels of Mux tree with merging case statements.It also simplifies the address logic to achieve a simpler address encoding circuit,hence optimizing the area and delay of the circuits after being mapped.The proposed algorithm is implemented in C++,and the optimization results are obtained using academic EDA tool named abc with the mapping library provided by domestic EDA companies.The experimental results show that compared with abc tool,the performance of area and delay are improved by 26%and 21%,respectively.

关 键 词：Mux树 case语句综合 逻辑优化 Verilog HDL 

分 类 号：TP391.41[自动化与计算机技术—计算机应用技术]