基于FPGA的多相IDFT数字信道化高效结构算法实现  

Implementation of Polyphase IDFT Digital Channel High-efficiency Structure Algorithm Based on FPGA

作　　者：孟辰[1] Meng Chen

机构地区：[1]中国电子科技集团公司第39研究所,西安710065

出　　处：《测控与通信》2023年第1期14-21,共8页

摘　　要：本文对数字信道化接收机的传统实现结构进行分析与研究,在此基础上基于多相滤波的原理进一步研究推导出1种基于多相IDFT(Inverse Discrete Fourier Transform)的数字信道化高效结构,并在实际的硬件平台中实现4~5GHz全频段、全概率覆盖,全子信道并行接收的数字信道化功能。通过实测数据与仿真数据的比对,验证其算法在工程上的可行性。This paper analyzed the traditional implementation structure of the digital channelized receiver.On this basis,a digital channelized efficient structure based on the principle of polyphase IDFT is further studied and deduced.And realize the digital channelization function of 4GHz~5GHz full frequency band,full probability coverage and full sub-channel parallel reception.In the actual hardware platform,through the comparison of measured data and simulation data,the engineering feasibility of the algorithm is verified.

关 键 词：数字信道化 多相滤波 FPGA IDFT 

分 类 号：TN9[电子电信—信息与通信工程]