基于硬件增强设计的高速ADC测试技术研究  

Research on Test Technology for High-Speed ADC Based on Hardware Enhanced Designs

作　　者：马士民 龙善丽 顾逸尘 徐福彬 李金雄 闫旭 张紫乾 MA Shimin;LONG Shanli;GU Yichen;XU Fubin;LI Jinxiong;YAN Xu;ZHANG Ziqian(East China Institute of Optoelectronic Integrated Devices,Suzhou Jiangsu 215163,China)

机构地区：[1]华东光电集成器件研究所,江苏苏州215163

出　　处：《电子器件》2023年第4期882-887,共6页Chinese Journal of Electron Devices

摘　　要：针对高速ADC的精准评价与降低硬件测试平台对ADC的性能损伤需求,通过对高速ADC测试平台硬件损伤的定性分析,对板级阻抗、输入衰减网络、通道间隔离度及数字输出对指标影响做理论推导。根据定性分析和理论指导,对高速ADC的硬件做增强型设计。以双通道1.5 GSPS,10位ADC实施增强设计及系统级验证,测试结果表明:输入链路阻抗、衰减网络的优化可获得0.6 dB链路增益;输入链路与时钟链路间隔离度优化获得>3 dB底噪收益;链路中串接功率补偿模块可明显抑制杂散。这为高速ADC性能的可靠评估提供了有效参考。To meet the need of accurate evaluation of high-speed ADC and to reduce the damage of hardware test platform on ADC per-formance,qualitative analysis of hardware damage of high-speed ADC test platform and theoretical derivation of board-level impedance,input attenuation network,inter-channel isolation and digital output impact on performance are performed.The hardware of high-speed ADC is enhanced according to the qualitative analysis and theoretical guidance.System-level verification of the enhanced schemes is carried out with a dual-channel 1.5 GSPS,10-bit ADC and the test results show that the optimization of the input channel impedance and attenuation network can obtain 0.6 dB chain gain,the optimization of the isolation between the input channel and the clock channel can achieve>3 dB noise floor gain,and the power compensation can suppress spurs obviously,providing efficient reference for reliable evaluation of high-speed ADC.

关 键 词：硬件增强 高速ADC 测试技术 

分 类 号：TN602[电子电信—电路与系统] TN606