HMAC-SM3/SHA256算法的低开销硬件结构设计  

A Low-Cost Hardware Architecture for HMAC-SM3/SHA256 Algorithms

作　　者：陈锐 李冰 朱家乐 刘向东 CHEN Rui;LI Bing;ZHU Jiale;LIU Xiangdong(School of Computer and Software Engineering,Nanjing Vocational University of Industry Technology,Nanjing Jiangsu 210023,China;School of Microelectronics,Southeast University,Nanjing Jiangsu 210035,China)

机构地区：[1]南京工业职业技术大学计算机与软件学院,江苏南京210023 [2]东南大学微电子学院,江苏南京210035

出　　处：《电子器件》2023年第4期888-894,共7页Chinese Journal of Electron Devices

基　　金：深圳市科技计划基础研究(学科布局)项目(JCYJ20170817115500476);南京工业职业技术大学校级科研项目(YK18-05-04,YK20-05-07);江苏省工业软件工程技术研究开发中心开放基金重点项目(ZK19-04-03)。

摘　　要：为了保障工业物联网设备采集数据的完整性,提出一种HMAC算法的通用硬件结构,并在此结构基础上,以资源复用的方式将SM3和SHA256算法与HMAC算法集成,实现同一块电路支持SM3、SHA256、HMAC-SM3和HMAC-SHA256四种算法。仿真结果显示,在10 MHz时钟频率下,吞吐率最高可达39.3 Mbps。FPGA实现结果表明,相对于单独实现四种算法,逻辑资源缩减53.3%,仅需占用3530个逻辑单元(Logic Element)和2240 bit的存储资源。In order to ensure the integrity of data collected by industrial internet of things(IIoT)devices,a general hardware architecture of the HMAC algorithm is proposed.On the basis of this architecture,the SM3 and SHA256 algorithms are integrated with the HMAC algorithm by means of resource-sharing,so that the same circuit supports four algorithms:SM3,SHA256,HMAC-SM3 and HMAC-SHA256.The simulation results show that the maximum throughput rate achieves up to 39.3 Mbps at a clock frequency of 10 MHz.FPGA implementation results show that compared to the separate implementation of these algorithms,logic resources are reduced by 53.3%,and only 3530 Logic Element(LE)and 2240 bits of memory resources are required.

关 键 词：数据完整性 SM3 SHA256 HMAC 物联网 硬件结构 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]