一种低抖动电流模自偏置锁相环设计  

Design of a low jitter current mode self-biased phase-locked loop

作　　者：曾勇 李海松[1] 尹飞[1] ZENG Yong;LI Haisong;YIN Fei(Xi’an Microelectronics Technology Institute,Xi’an 710054,China)

机构地区：[1]西安微电子技术研究所,陕西西安710054

出　　处：《微电子学与计算机》2023年第9期75-82,共8页Microelectronics & Computer

摘　　要：基于28 nm CMOS工艺,设计了一款新型电流模自偏置锁相环.重点分析了电荷泵、电压转电流(V-I)模块、电流型数模转换器(Digital to Analog Converter,DAC)及电流控制振荡器(Current-Controlled Oscillator,CCO)的电路设计和功能.采用电流复制反馈偏置(Replica Feedback Bias)技术,实现了带宽自适应,利用可编程的DAC模块降低了输入范围对于系统稳定性的影响,消除分配范围对于环路稳定性的影响,利用前分频器进一步拓宽输入频率范围,实现了宽输入输出频率范围及低抖动电流模锁相环的设计.整体芯片面积为0.07462 mm^(2),采用双电源供电1.8 V/0.9 V,最大功耗为10 mW,输出频率为1 GHz~3.2 GHz.仿真测试结果表明,输入参考频率为50 MHz时,在2.1 GHz中心频率1 MHz频偏处的相位噪声为−98.18 dBc/Hz,rms抖动为1.914 ps.Based on 28 nm CMOS process,a new current mode self-biased phase-locked loop is designed.The circuit design and functions of charge pump,voltage to current(V-I)module,current mode Digital to Analog Converter(DAC)and Current Controlled Oscillator(CCO)are analyzed in detail.The technology of Replica Feedback Bias is adopted to realize bandwidth adaptation.The programmable IDAC module is used to reduce the impact of the input range on the system stability and eliminate the impact of the allocation range on the loop stability.The front divider is used to further expand the input frequency range and realize the design of a wide input and output frequency range and a low jitter current mode phase-locked loop.The overall chip area is 0.07462 mm^(2),the dual power supply is used to supply 1.8 V/0.9 V,the maximum power consumption is 10 mW,and the output frequency is 1 GHz~3.2 GHz.The simulation test results show that when the input reference frequency is 50 MHz,the phase noise at the center frequency 1 MHz offset of 2.1 GHz is−98.18 dBc/Hz,and the rms jitter is 1.914 ps.

关 键 词：锁相环 自偏置 电流模 低抖动 

分 类 号：TN761[电子电信—电路与系统]