一种可配置异构多核SoC的设计实现方法  

Design Method of Configurable Heterogeneous Multi-core SoC

作　　者：潘斌 Pan Bin(Southern Power Grid Guangdong Zhongshan Power Supply Bureau,Zhongshan 528400,China)

机构地区：[1]南方电网广东中山供电局,中山528400

出　　处：《单片机与嵌入式系统应用》2023年第9期20-23,共4页Microcontrollers & Embedded Systems

基　　金：国家自然科学基金(61472458)。

摘　　要：针对需要高性能处理和低功耗的各种应用(识别、推理、测量、控制和安全),开发了一种多核片上系统(System-on-Chip,SoC)。该SoC集成了3种可综合的处理器:8个CPU(M32R)、2个多组矩阵处理器(Multi-Bank Matrix processors,MBMX)和1个控制器(M32C)。这些处理器分别以1 GHz、500 MHz和500 MHz的频率运行,这3种处理器通过高带宽多层系统总线在芯片上相互连接,8个CPU通过缓存一致性机制连接到一个公共流水线总线上。此外,8个CPU共享1个512 KB的L2缓存以减少内部总线流量,采用了一种具有2读1写计算和后台I/O操作功能的多组矩阵处理器,1 GHz的CPU通过延迟管理网络实现,该网络包括可以适用于任何应用或工艺技术的延迟监视器。可配置异构架构具有9个CPU和2个矩阵处理器,可以将功耗降低45%。A system-on-chip(SoC)has been developed in this study to cater to various applications requiring high-performance processing and low power consumption,such as recognition,in-ference,measurement,control,and security.The SoC integrates three synthesizable processors:eight CPUs(M32R),two multi-bank matrix processors(MBMX),and one controller(M32C).These processors operate at frequencies of 1 GHz,500 MHz,and 500 MHz respectively.The three processors are interconnected on the chip through a high-bandwidth multi-layer system bus.The eight CPUs are connected to a shared pipeline bus via a cache coherence mechanism.Additionally,the eight CPUs share a 512 KB L2 cache to reduce internal bus traffic.The multi-bank matrix processor,which features 2-read-1-write computation and background I/O operations,is implemented using a 1 GHz CPU and a delay management network.This network includes a delay monitor applicable to any application or process technology.The configurable heterogeneous architecture comprises nine CPUs and two matrix processors,enabling a 45%reduction in power consumption.

关 键 词：时钟延迟调整器 CMOS 可配置处理器 延迟监视器 异构多核处理器 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]